933977630512 NXP Semiconductors, 933977630512 Datasheet - Page 14

• Manufacturer Part Number: 933977630512
• Manufacturer: NXP Semiconductors

Specifications of 933977630512

• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage (typ): 5V
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Pin Count: 44
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Supply Current: 10mA
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Compliant

applied via CRB. After reading or writing MR1B, the pointer will point
Philips Semiconductors
Table 2.
MR2A[3:0] – Channel A Stop Bit Length Select
This field programs the length of the stop bit appended to the
transmitted character. Stop bit lengths of 9/16 to 1 and 1–9/16 to
2 bits, in increments of 1/16 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1–1/16
to 2 stop bits can be programmed in increments of 1/16 bit. In all
cases, the receiver only checks for a ‘mark’ condition at the center
of the first stop bit position (one bit time after the last data bit, or
after the parity bit is enabled).
If an external 1X clock is used for the transmitter, MR2A[3] = 0
selects one stop bit and MR2A[3] = 1 selects two stop bits to be
transmitted.
MR1B – Channel B Mode Register 1
MR1B is accessed when the Channel B MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
to MR2B.
The bit definitions for this register are identical to MR1A, except that
all control actions apply to the Channel B receiver and transmitter
and the corresponding inputs and outputs.
MR2B – Channel B Mode Register 2
MR2B is accessed when the Channel B MR pointer points to MR2,
which occurs after any access to MR1B. Accesses to MR2B do not
change the pointer.
2004 Mar 03
Dual asynchronous receiver/transmitter (DUART)
CTUR
CTLR
IPCR
IMR
ISR
IVR
Register Bit Formats
CHANGE
CHANGE
IN PORT
IN PORT
0 = No
1 = Yes
0 = No
1 = Yes
0 = Off
1 = On
C/T[15]
DELTA
IVR[7]
C/T[7]
BIT 7
BIT 7
BIT 7
BIT 7
BIT 7
BIT 7
INT
IP3
BREAK B
BREAK B
0 = No
1 = Yes
0 = No
1 = Yes
0 = Off
1 = On
C/T[14]
DELTA
DELTA
DELTA
IVR[6]
C/T[6]
BIT 6
BIT 6
BIT 6
BIT 6
BIT 6
BIT 6
INT
IP2
(Continued)
FFULLB
FFULLB
0 = No
1 = Yes
RxRDY/
0 = No
1 = Yes
RxRDY/
0 = Off
1 = On
C/T[13]
DELTA
C/T[5]
IVR[5]
BIT 5
BIT 5
BIT 5
BIT 5
BIT 5
BIT 5
INT
IP1
TxRDYB
TxRDYB
0 = No
1 = Yes
0 = No
1 = Yes
0 = Off
1 = On
C/T[12]
DELTA
C/T[4]
IVR[4]
BIT 4
BIT 4
BIT 4
BIT 4
BIT 4
BIT 4
14
IP0
INT
The bit definitions for mode register are identical to the bit definitions
for MR2A, except that all control actions apply to the Channel B
receiver and transmitter and the corresponding inputs and outputs.
Table 3.
NOTE: The receiver clock is always a 16X clock except for CSRA[7:4] = 1111.
CSRA[7:4]
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
COUNTER
COUNTER
0 = LOW
1 = HIGH
0 = No
1 = Yes
0 = Off
1 = On
READY
READY
C/T[11]
IVR[3]
C/T[3]
BIT 3
BIT 3
BIT 3
BIT 3
BIT 3
BIT 3
INT
IP3
Baud Rate
IP4–16X
ACR[7] = 0
IP4–1X
134.5
1,200
1,050
2,400
4,800
7,200
9,600
Timer
38.4k
200
300
600
BREAK A
BREAK A
110
0 = LOW
1 = HIGH
0 = No
1 = Yes
0 = Off
1 = On
50
C/T[10]
DELTA
DELTA
IVR[2]
C/T[2]
BIT 2
BIT 2
BIT 2
BIT 2
BIT 2
BIT 2
INT
IP2
Baud Rate ACR[7] = 1
FFULLA
FFULLA
0 = LOW
1 = HIGH
RxRDY/
0 = No
1 = Yes
RxRDY/
0 = Off
1 = On
C/T[9]
C/T[1]
IVR[1]
BIT 1
BIT 1
BIT 1
BIT 1
BIT 1
BIT 1
INT
IP1
IP4–16X
SCC68692
IP4–1X
134.5
1,200
2,000
2,400
4,800
1,800
9,600
Timer
19.2k
150
300
600
110
75
Product data
TxRDYA
TxRDYA
0 = LOW
1 = HIGH
0 = No
1 = Yes
0 = Off
1 = On
C/T[8]
C/T[0]
IVR[0]
BIT 0
BIT 0
BIT 0
BIT 0
BIT 0
BIT 0
IP0
INT