XR88C681CP/40 Exar Corporation, XR88C681CP/40 Datasheet - Page 88

• Manufacturer Part Number: XR88C681CP/40
• Description: Dual Channel UART
• Manufacturer: Exar Corporation

Specifications of XR88C681CP/40

• Features: *
• Number Of Channels: 2, DUART
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

H.3 Standby Mode
The DUART may be placed in a standby mode to
conserve power when its operation is not required. Upon
reset, the DUART will be in the “ACTIVE OPERATION”
mode. A “SET STANDBY MODE” command issued via
the channel A Command Register disables all clocks on
the device except for the crystal oscillator, which
significantly reduces the operating current. In this mode
that only functions which will operate correctly are reading
the input port, writing the output port and the “SET
ACTIVE MODE” command. The latter, also invoked via
the Channel A Command register, restores the device to
normal operation within 25 s. Resetting the transmitters
and receivers and writing 00h into the IMR (Interrupt Mask
Register) before going into the Standby mode is
recommended to prevent any spurious interrupts from
being generated. The chip should be reprogrammed after
the “SET ACTIVE MODE” command since register
contents are not guaranteed to remain stable during the
standby mode. Active operation can also be restored via
hardware reset.
I. COMMENTS ABOUT THE XR88C681 IN 28 PIN
Much of this data sheet discussed features which are
available to the DUARTs which are packaged in the 40 pin
DIP or the 44 pin PLCC. However, because of the
reduced number of pins the DUARTs in the 28 pin
package do not have the following features.
REGISTER SUMMARY
DIP PACKAGE
Rx RTS
Control
1 = Yes
0 = No
Rev. 2.11
Bit 7
Rx Int Select
0=RXRDY
1=FFULL
Bit 6
Error Mode
0= Char.
1= Block
Bit 5
Table 29. Mode Registers 1: MR1A, MR1B
Parity Mode
11 = Multi-Drop Mode
Bit 4
01 = Force Parity
00 = With Parity
10 = No Parity
88
D Cannot operate in the Z-Mode
D Cannot perform modem shaking functions
J. PROGRAMMING
Operation of the DUART is programmed by writing control
words into the appropriate registers, while operational
feedback is provided by status registers which can be read
by the CPU. Register addressing is shown in .
A hardware reset clears the contents of the SRn, IMR,
ISR, OPR, and OPCR registers and initializes the IVR to
0F
contents of control registers are to be changed, since
certain changes may result in improper operation.
For Example:
Changing the number of bits per character while data is
being received may result in reception of erroneous
character. In general, changes to registers which control
receiver or transmitter operation should be made only
while the transmitter or receiver are disabled, and certain
changes to the ACR should be made only when the C/T is
stopped.
Mode, command, clock select, and status registers are
duplicated for each channel to provide total independent
operation. Table 29 through Table 41 summarizes the bit
assignments for each register.
Select
16
Bit 3
This is due to lack of the
This is due to the lack of any CTS pins
. During operation, care should be exercised if the
0 = Even
1 = Odd
Select
Parity
Bit 2
-
IACK, IEI, and IEO pins
Number of Bits/Char.
Bit 1
00 = 5
01 = 6
10 = 7
11 = 8
Bit 0