STM8L152R6T6 STMicroelectronics, STM8L152R6T6 Datasheet - Page 60

• Manufacturer Part Number: STM8L152R6T6
• Description: 8 BITS MICROCONTR
• Manufacturer: STMicroelectronics
• Series: STM8L EnergyLiter

Specifications of STM8L152R6T6

• Core Processor: STM8
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, IR, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 28x12b, D/A 2x12
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Option bytes
7
Table 12.
60/126
Address
00 480C
00 480A
00 480B
00 4800
00 4802
00 4807
00 4808
00 4809
Boot code size)
clock cycles for
Brownout reset
Option name
HSE and LSE
PCODESIZE
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated memory block.
All option bytes can be modified in ICP mode (with SWIM) by accessing the EEPROM
address. See
The option bytes can also be modified ‘on the fly’ by the application in IAP mode, except for
the ROP, UBC and PCODESIZE values which can only be taken into account when they are
modified in ICP mode (with the SWIM).
Refer to the STM8L15x/STM8L16x Flash programming manual (PM0054) and STM8 SWIM
and Debug Manual (UM0320) for information on SWIM programming procedures.
Option byte addresses
Independent
option bytes
stabilization
Bootloader
Number of
UBC (User
oscillators
protection
watchdog
Read-out
(OPTBL)
(ROP)
(BOR)
option
Table 12
OPTBL
Option
OPT0
OPT1
OPT2
OPT3
OPT4
OPT5
[15:0]
byte
[3:0]
[3:0]
No.
for details on option byte addresses.
7
Doc ID 17943 Rev 4
Reserved
Reserved
Reserved
6
5
4
OPTBL[15:0]
PCODE[7:0]
Option bits
ROP[7:0]
UBC[7:0]
WWDG
_HALT
LSECNT[1:0]
3
BOR_TH
WWDG
_HW
2
STM8L15xx8, STM8L15xR6
_HALT
IWDG
HSECNT[1:0]
1
IWDG
BOR_
_HW
ON
0
Factory
default
setting
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00