STK12C68-5K55M Cypress Semiconductor Corp, STK12C68-5K55M Datasheet - Page 2

• Manufacturer Part Number: STK12C68-5K55M
• Description: STK12C68-5K55M
• Manufacturer: Cypress Semiconductor Corp

Specifications of STK12C68-5K55M

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 64K (8K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 28-CDIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pinouts
Pin Definitions
Document Number: 001-51026 Rev. **
Pin Name
DQ
A
V
HSB
0
V
V
WE
CE
OE
0
–A
CAP
SS
CC
-DQ
12
7
Alt
W
G
E
Figure 1. Pin Diagram - 28-Pin DIP
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in
Power Supply Power Supply Inputs to the Device.
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
IO Type
Ground
Input
Input
Input
Input
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground for the Device. The device is connected to ground of the system.
progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A
weak internal pull up resistor keeps this pin high if not connected (connection optional).
to nonvolatile elements.
Description
STK12C68-5 (SMD5962-94599)
Figure 2. Pin Diagram - 28-Pin LLC
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