SST89E58RD2-40-C-TQJE Microchip Technology, SST89E58RD2-40-C-TQJE Datasheet
SST89E58RD2-40-C-TQJE
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SST89E58RD2-40-C-TQJE Summary of contents
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... Automatic Address Recognition • Ten Interrupt Sources at 4 Priority Levels – Four External Interrupt Inputs PRODUCT DESCRIPTION The SST89E54RD2A/RDA and SST89E58RD2A/RDA are members of the FlashFlex family of 8-bit microcontroller products designed and manufactured with SST patented and proprietary SuperFlash CMOS semiconductor pro- cess technology ...
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... Full-Duplex, Enhanced UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.0 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.0 PROGRAMMABLE COUNTER ARRAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.1 PCA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.2 PCA Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.3 Compare/Capture Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.0 SECURITY LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.1 Hard Lock ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA 2 FlashFlex MCU S71339-02-000 02/08 ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA 9.2 SoftLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.3 Security Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.4 Read Operation Under Lock Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.0 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.2 Software Reset 10.3 Brown-out Detection Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.0 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.1 Interrupt Priority and Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.0 POWER-SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12 ...
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... FIGURE 14-12: I Test Condition Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 DD FIGURE 16-1: 40-Pin Plastic Dual In-line Pins (PDIP FIGURE 16-2: 44-Lead Plastic Lead Chip Carrier (PLCC FIGURE 16-3: 44-Lead Thin Quad Flat Pack (TQFP ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA 4 FlashFlex MCU S71339-02-000 02/08 ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA LIST OF TABLES TABLE 2-1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TABLE 3-1: SFCF Values for Program Memory Block Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TABLE 3-2: SFCF Values Under Different Reset Conditions TABLE 3-3: External Data Memory RD#, WR# with EXTRAM bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 3-4: FlashFlex SFR Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TABLE 3-5: CPU related SFRs ...
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... Block 16K/32K x8 Secondary Block 8K x8 Timer 0 (16-bit) Timer 1 (16-bit) Timer 2 (16-bit) FIGURE 1-1: Functional Block Diagram ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA 8051 CPU Core ALU, ACC, B-Register, Instruction Register, Program Counter, Timing and Control Flash Control Unit RAM 1K x8 ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA 2.0 PIN ASSIGNMENTS (CEX1 / SS#) P1.4 (CEX2 / MOSI) P1.5 (CEX3 / MISO) P1.6 (CEX4 / SCK) P1.7 FIGURE 2-1: Pin Assignments for 40-pin PDIP ©2008 Silicon Storage Technology, Inc (T2) P1 P0.0 (AD0) (T2 EX) P1 P0.1 (AD1) (ECI) P1 P0.2 (AD2) (CEX0) P1.3 ...
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... MOSI) P1.5 (CEX3 / MISO) P1.6 (CEX4 / SCK) P1.7 (RXD) P3.0 INT2#/P4.3 (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) ?P3.5 FIGURE 2-2: Pin Assignments for 44-lead TQFP ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA RST 4 5 44-lead TQFP 6 Top View 7 8 ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA (CEX2 / MOSI) P1.5 (CEX3 / MISO) P1.6 (CEX4 / SCK) P1.7 RST (RXD) P3.0 INT2#/P4.3 (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5 FIGURE 2-3: Pin Assignments for 44-lead PLCC ©2008 Silicon Storage Technology, Inc 44-lead PLCC Top View ...
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... RXD: Universal Asynchronous Receiver/Transmitter (UART) - Receive input P3[1] O TXD: UART - Transmit output ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA Port 0 also receives the code bytes during the external host mode OH. . Port 2 also receives some control signals and high-order address bits during the exter- 10 ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA TABLE 2-1: Pin Descriptions (Continued Symbol Type Name and Functions P3[2] I INT0#: External Interrupt 0 Input P3[3] I INT1#: External Interrupt 1 Input P3[4] I T0: External count input to Timer/Counter 0 P3[5] I T1: External count input to Timer/Counter 1 P3[6] O WR#: External Data Memory Write strobe ...
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... FIGURE 3-1: Program Memory Organization for 16 KByte SST89E54RDxA ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA bank selection. Please refer to Figures 3-1 and 3-2 for the program memory configuration. Program bank selection is described in the next section. The 16K/32K x8 primary SuperFlash block is organized as 128/256 sectors, each sector consists of 128 Bytes ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA EA FFFFH External 64 KByte 0000H FIGURE 3-2: Program Memory Organization for 32 KByte SST89E58RDxA 3.2 Program Memory Block Switching The program memory block switching feature of the device allows either Block 1 or the lowest 8 KByte of Block used for the lowest 8 KByte of the program address space. SFCF[1:0] controls program memory block switching. ...
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... SFRs space are physically separate even though they have the same addresses. ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA When instructions access addresses in the upper 128 bytes (above 7FH), the MCU determines whether to access the SFRs or RAM by the type of instruction given indirect, then RAM is accessed ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA read and write signals (P3.6 - WR# and P3.7 - RD#) for external memory use. Table 3-3 shows external data mem- ory RD#, WR# operation with EXTRAM bit. TABLE 3-3: External Data Memory RD#, WR# with EXTRAM bit MOVX @DPTR MOVX A, @DPTR AUXR ADDR < ...
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... RAM 768 Bytes (Indirect Addressing) 000H 2FFH Expanded RAM 000H FIGURE 3-3: Internal and External Data Memory Structure ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA FFH FFH (Indirect Addressing) Upper 128 Bytes Internal RAM 80H 80H 7FH Lower 128 Bytes Internal RAM (Indirect & ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA 3.5 Dual Data Pointers The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS=0, DPTR0 is selected; when DPS=1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1. (See Figure 3-4) ...
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... B2H SFCM SuperFlash Command B3H SFAL SuperFlash Address Low B4H SFAH SuperFlash Address High B5H SFDT SuperFlash Data ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA Bit Address, Symbol, or Alternative Port Function MSB ACC[7:0] B[7: RS1 RS0 SP[7:0] DPL[7:0] DPH[7: ET2 ES ET1 ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA TABLE 3-6: Flash Memory Programming SFRs Direct Symbol Description Address B6H SFST SuperFlash Status ©2008 Silicon Storage Technology, Inc. Bit Address, Symbol, or Alternative Port Function MSB SB1_i SB2_i SB3_i - EDC_i 19 Data Sheet Reset LSB Value FLASH_BUSY - - 000x00xxb T3-6 ...
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... CBH RCAP2H Timer 2 Capture MSB CAH RCAP2L Timer 2 Capture LSB 1. Bit Addressable SFRs Don’t care ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA Bit Address, Symbol, or Alternative Port Function MSB - - - WDOUT WDRE Watchdog Timer Data/Reload Bit Address, Symbol, or Alternative Port Function ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA TABLE 3-9: Interface SFRs Direct Symbol Description Address 99H SBUF Serial Data Buffer 98H 1 SCON Serial Port Control A9H SADDR Slave Address B9H SADEN Slave Address Mask D5H SPCR SPI Control Register AAH SPSR SPI Status Register ...
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... DAH CCAPM0 PCA Compare/Capture DBH CCAPM1 Module Mode DCH CCAPM2 Registers DDH CCAPM3 DEH CCAPM4 1. Bit Addressable SFRs ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA Bit Address, Symbol, or Alternative Port Function MSB CH[7:0] CL[7: CCF4 CCF3 CCF2 CIDL WDTE - - CCAP0H[7:0] CCAP0L[7:0] ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA SuperFlash Configuration Register (SFCF) Location 7 6 B1H - IAPEN Symbol Function IAPEN Enable IAP operation 0: IAP commands are disabled 1: IAP commands are enabled SWR Software Reset See Section 10.2, “Software Reset” BSEL Program memory block switching bit ...
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... Double Clock Status clocks per machine cycle 1: 6 clocks per machine cycle FLASH_BUSY Flash operation completion polling bit. 0: Device has fully completed the last IAP command. 1: Device is busy with flash operation. ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA SuperFlash Data Register ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA Interrupt Enable (IE) Location 7 6 A8H EA EC Symbol Function EA Global Interrupt Enable Disable 1 = Enable EC PCA Interrupt Enable. ET2 Timer 2 Interrupt Enable. ES Serial Interrupt Enable. ET1 Timer 1 Interrupt Enable. EX1 External 1 Interrupt Enable. ET0 Timer 0 Interrupt Enable. EX0 External 0 Interrupt Enable. ...
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... Interrupt Priority 1 High (IP1H) Location 7 6 F7H 1 - Symbol Function PBOH Brown-out Interrupt priority bit high PX2H External Interrupt 2 priority bit high PX3H External Interrupt 3 priority bit high ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA PT2 PS PT1 PX1 PT2H PSH PT1H PX1H 5 ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA Auxiliary Register (AUXR) Location 7 6 8EH - - Symbol Function EXTRAM Internal/External RAM access 0: Internal Expanded RAM access within range of 00H to 2FFH using MOVX @Ri / @DPTR. Beyond 300H, the MCU always accesses external data memory. For details, refer to Section 3.4, “Expanded Data RAM Addressing” . ...
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... Must be cleared by software. CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA Watchdog Timer Data/Reload 1 (CCON) ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA PCA Timer/Counter Mode Register Location 7 6 D9H CIDL WDTE 1. Not bit addressable Symbol Function CIDL Counter Idle Control: 0: Programs the PCA Counter to continue functioning during idle mode 1: Programs the PCA Counter to be gated off during idle WDTE ...
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... Enables CEXn pin to be used as a pulse width modulated output ECCFn Enable CCF Interrupt 0: Disables compare/capture flag CCF[4:0] in the CCON register to generate an interrupt request. 1: Enables compare/capture flag CCF[4:0] in the CCON register to generate an interrupt request. ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA 1 (CCAPMn CAPP0 CAPN0 ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA SPI Control Register (SPCR) Location 7 6 D5H SPIE SPE Symbol Function SPIE If both SPIE and ES are set to one, SPI interrupts are enabled. SPE SPI enable bit. 0: Disables SPI. 1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1.4, P1.5, P1.6, P1.7. ...
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... Power-down bit, this bit is cleared by hardware after exiting from power-down mode. 0: Power-down mode is not activated. 1: Activates Power-down mode. IDL Idle mode bit, this bit is cleared by hardware after exiting from idle mode. 0: Idle mode is not activated. 1: Activates idle mode. ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA SPDR[7: ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA Serial Port Control Register (SCON) Location 7 6 98H SM0/FE SM1 Symbol Function FE Set SMOD0 = 1 to access FE bit framing error 1: Framing Error. Set by receiver when an invalid stop bit is detected. This bit needs to be cleared by software. SM0 SMOD0 = 0 to access SM0 bit. ...
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... Note: User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate. T2OE Timer 2 Output Enable bit. DCEN Down Count Enable bit. When set, this allows Timer configured as an up/down counter. ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA RCLK TCLK EXEN2 ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA External Interrupt Control (XICON) Location 7 6 AEH X EX3 Symbol Function X Don’t Care EX2 External Interrupt 2 Enable bit if set IE2 Interrupt Enable If IT2=1, IE2 is set/cleared automatically by hardware when interrupt is detected/ serviced. IT2 External Interrupt 2 is falling-edge/low-level triggered when this bit is cleared by software ...
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... Block 1 memory to be overlaid on the lowest 8 KByte of Block 0 memory, making Block 1 reachable. The ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA same concept is employed to allow both Block 0 and Block 1 flash to be accessible to IAP operations. Code from a block that is not visible may not be used as a source to pro- gram another address. However, a block that is not “ ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA 4.2.4.1 Chip-Erase The Chip-Erase command erases all bytes in both memory blocks. This command is only allowed when EA#=0 (exter- nal memory execution). Additionally this command is not permitted when the device is in level 4 locking. In all other instances, this command ignores the Security Lock status and will erase the security lock bits and re-map bits ...
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... MOV SFCM, #8FH FIGURE 4-6: Prog-SB3, Prog-SB2, Prog-SB1 ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA that the previous flash operation has fully completed before issuing a Byte-Verify. Byte-Verify command execution time is short enough that there is no need to poll for command completion and no interrupt is generated. ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA 4.2.4.7 Prog-SC0, Prog-SC1 Prog-SC0 command is used to program the SC0 bit. This command only changes the SC0 bit and has no effect on BSEL bit until after a reset cycle. SC0 bit previously in un-programmed state can be pro- grammed by this command. The Prog-SC0 command should reside only in Block 1 or external code memory ...
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... T2. Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. There- fore, bit TR2 must be set separately to turn the timer on. ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA 2 SFDT [7:0] 01H 55H 0DH ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA TABLE 5-2: Timer/Counter 1 Mode Function 0 13-bit Timer 1 16-bit Timer Used as Timer 2 8-bit Auto-Reload 3 Does not run 0 13-bit Timer 1 16-bit Timer Used as Counter 2 8-bit Auto-Reload 3 Not available 1. The Timer is turned ON/OFF by setting/clearing bit TR1 in the software. 2. The Timer is turned ON/OFF by the transition on INT1# (P3 ...
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... SMOD1 SMOD0 FIGURE 6-1: Framing Error Block Diagram ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA SCON register is set. Reception is initiated in the other modes by the incoming start bit if the REN bit of the SCON register is set. 6.1.1 Framing Error Detection Framing Error Detection is a feature, which allows the receiving controller to check for valid stop bits in modes ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA RXD D0 Start bit RI SMOD0=X FE SMOD0=1 FIGURE 6-2: UART Timings in Mode 1 RXD D0 Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 FIGURE 6-3: UART Timings in Modes 2 and 3 ©2008 Silicon Storage Technology, Inc Data byte Data byte 43 Data Sheet D7 Stop bit 1339 F17.0 ...
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... Slave 1 SADDR = 1111 0001 SADEN = 1111 1010 GIVEN = 1111 0X0X ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA Slave 2 SADDR = SADEN = GIVEN = 1111 0XX1 6.1.2.1 Using the Given Address to Select Slaves Any bits masked off from SADEN become a “don’t care” bit for the given address. Any bit masked off becomes ANDED with SADDR. The “ ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA The user could use the possible addresses above to select slave 3 only. Another combination could be to select slave 2 and 3 only as shown below. Select Slaves 2 and 3 Only Slaves 2 and 3 Possible Addresses 1111 0011 More than one slave may have the same SADDR address as well, and a given address could be used to modify the address so that it is unique ...
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... SS# (to Slave) FIGURE 6-5: SPI Transfer Format with CPHA = 0 SCK Cycle # 1 (for reference) SCK (CPOL=0) SCK (CPOL=1) MOSI MSB (from Master) MISO MSB (from Slave) SS# (to Slave) FIGURE 6-6: SPI Transfer Format with CPHA = 1 ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA 7.0 WATCHDOG TIMER The device offers a programmable Watchdog Timer (WDT) for fail safe protection against software deadlock and auto- matic recovery. To protect the system against software deadlock, the user software must refresh the WDT within a user-defined time period ...
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... PCA Timer/Counter FIGURE 8-1: PCA Timer/Counter and Compare/Capture Modules ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA PCA. External events associated with modules are shared with corresponding Port 1 pins. Modules not using the port pins can still be used for standard I/O. Each of the five modules can be programmed in any of the following modes: • ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA The table below summarizes various clock inputs at two common frequencies. TABLE 8-2: PCA Timer/Counter Inputs PCA Timer/Counter Mode Mode 0: f /12 OSC Mode 1: 1 Mode 2: Timer 0 Overflows Timer 0 programmed in: 8-bit mode 16-bit mode 8-bit auto-reload Mode 3: External Input MAX 1 ...
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... EEH CCAP4L Registers ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA Bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) deter- mine whether the capture input will be active on a positive edge or negative edge. The CAPN bit enables the negative edge that a capture input will be active on, and the CAPP bit enables the positive edge ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA TABLE 8-5: PCA Module Modes Without Interrupt enabled ECOMy CAPPy CAPNy MATy - User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate disables toggle function enables toggle function on CEX[4:0] pin. 4. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal. ...
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... FIGURE 8-2: PCA Capture Mode ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA and CL) into the module’s capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set, then an interrupt will be generated ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA 8.3.2 16-Bit Software Timer Mode The 16-bit software timer mode is used to trigger interrupt routines, which must occur at periodic intervals setup by setting both the ECOM and MAT bits in the module’s CCAPMn register. The PCA timer will be compared to the module’ ...
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... FIGURE 8-4: PCA High Speed Output Mode ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA High speed output mode is much more accurate than tog- gling pins since the toggle occurs before branching to an interrupt. In this case, interrupt latency will not affect the accuracy of the output ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA 8.3.4 Pulse Width Modulator The Pulse Width Modulator (PWM) mode is used to gener- ate 8-bit PWMs by comparing the low byte of the PCA timer (CL) with the low byte of the compare register (CCAPnL). When CL < CCAPnL the output is low. When CL ≥ ...
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... Thus, in most application the first solution is the best option. ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA Use the code below to initialize the Watchdog Timer. Mod- ule 4 can be configured in either compare mode, and the WDTE bit in CMOD must also be set. The user’s software then must periodically change (CCAP4H, CCAP4L) to keep a match from occurring with the PCA timer (CH, CL) ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA Write to Reset CCAP4L Write to CCAP4H CCAP4H 1 0 Enable FIGURE 8-6: PCA Watchdog Timer (Module 4 only) ©2008 Silicon Storage Technology, Inc. CIDL WDTE CCAP4L Module 4 Match 16-bit Comparator CH CL PCA Timer/Counter ECOMn CAPPn CAPNn MATn Data Sheet CPS1 ...
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... Note Programmed (Bit logic state = 0 Unprogrammed (Bit logic state = 1 Not Locked Hard locked Soft locked ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA issued through the command mailbox register, SFCM, exe- cuted from a Locked (hard locked or soft locked) block, can be operated on a soft locked block: Block-Erase, Sector- Erase, Byte-Program and Byte-Verify ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA TABLE 9-1: Security Lock Options Security Lock Bits Level SFST[7:5] SB1 1 000 U 2 100 P 3 011 U 101 P 010 U 110 P 001 U 4 111 Programmed (Bit logic state = 0 Unprogrammed (Bit logic state = 1). 2. SFST[7:5] = Security Lock Status Bits (SB1_i, SB2_i, SB3_i) 9 ...
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... Location of MOVC or IAP instruction 2. Target address is the location of the byte being read 3. External host Byte-Verify access does not depend on a source address. ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA Byte-Verify Allowed Source Target 1 2 Address Address ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA 10.0 RESET A system reset initializes the MCU and begins program execution at program memory location 0000H. The reset input for the device is the RST pin. In order to reset the device, a logic level high must be applied to the RST pin for at least two machine cycles (24 clocks), after the oscillator becomes stable ...
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... TF0 T0 IE1 Ext. Int1 TF1 T1 CF/CCFn PCA IE2 Ext. Int. 2 IE3 Ext. Int. 3 TI/RI/SPIF UART/SPI TF2, EXF2 T2 ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA Vector Interrupt Interrupt Address Enable Priority 0003H EX0 PX0/H 004BH EBO PBO/H 000BH ET0 PT0/H 0013H EX1 ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA 0 INT0# IT0 1 BOF TF0 0 INT1# IT1 1 TF1 ECF CF CCFn ECCFn 0 INT2# IT2 1 0 INT3# IT3 SPIF SPIE TF2 EXF2 INDIVIDUAL ENABLES FIGURE 11-1: Interrupt Structure ©2008 Silicon Storage Technology, Inc. IP/IPH/IPA/IPAH IE & IEA REGISTERS REGISTERS IE0 IE1 ...
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... Mode (Set PD bit in PCON) MOV PCON, #02H; ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA 12.2 Power-down Mode The power-down mode is entered by setting the PD bit in the PCON register. In the power-down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA 13.0 SYSTEM CLOCK AND CLOCK OPTIONS 13.1 Clock Input Options and Recom- mended Capacitor Values for Oscillator Shown in Figure 13-1 are the input and output of an inter- nal inverting amplifier (XTAL1, XTAL2), which can be con- figured for use as an on-chip oscillator. ...
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... Supply Voltage DD SST89E5xRD2A/RDA f Oscillator Frequency OSC SST89E5xRD2A/RDA Oscillator Frequency for IAP SST89E5xRD2A/RDA ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1. 25° 1. 260°C for 10 seconds ° C capable in both non-Pb and with-Pb solder versions. ° C for 10 seconds; please consult the factory for the latest information. ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA TABLE 14-2: Reliability Characteristics Symbol Parameter 1 N Endurance END 1 T Data Retention Latch Up LTH 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 14-3: AC Conditions of Test Input Rise/Fall Time . . . . . . . . . . . . . . . 10 ns Output Load ...
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... RST Pull-down Resistor RST 6 C Pin Capacitance IO I Power Supply Current DD IAP Mode @ 40 MHz Active Mode @ 40 MHz Idle Mode @ 40 MHz Power-down Mode ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA = 4.5-5.5V Test Conditions 4.5 < V < 5.5 DD 4.5 < V < 5.5 DD 4.5 < V < 5 4.5V ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA 1. Under steady state (non-transient) conditions, I Maximum I per port pin: 15mA OL Maximum I per 8-bit port:26mA OL Maximum I total for all outputs:71mA exceeds the test condition Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the V due to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > ...
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... Write Pulse Width (WE#) WLWH T RD# Low to Valid Data In RLDV T Data Hold After RD# RHDX T Data Float After RD# RHDZ T ALE Low to Valid Data In LLDV T Address to Valid Data In AVDV ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA = 4.5-5.5V@40MHz Oscillator 40 MHz (x1 Mode) 20 MHz (x2 Mode) Min Max CLCL ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA TABLE 14-7: AC Electrical Characteristics (Continued -40°C to +85° Symbol Parameter T ALE Low to RD# or WR# Low LLWL T Address to RD# or WR# Low AVWL T Data Hold After WR# WHQX T Data Valid to WR# High QVWH T Data Valid to WR# High to Low QVWX Transition ...
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... FIGURE 14-2: External Program Memory Read Cycle T LHLL ALE PSEN# RD# T AVLL A0-A7 FROM RI or DPL PORT 0 PORT 2 FIGURE 14-3: External Data Memory Read Cycle ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA T PLPH T T AVLL LLIV T T LLPL PLIV T T PLAZ ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA T LHLL ALE PSEN# WR# T AVLL A0-A7 FROM RI or DPL PORT 0 PORT 2 FIGURE 14-4: External Data Memory Write Cycle TABLE 14-8: External Clock Drive Symbol Parameter 1/T Oscillator Frequency CLCL T CLCL T High Time CHCX T Low Time CLCX T Rise Time ...
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... DD V (0.45V) for a Logic “0”. Measurement reference points for inputs and ILT outputs are at V (0.2V + 0.9) and V (0. FIGURE 14-7: AC Testing Input/Output Test Waveform ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA 40MHz Min Max 0.3 117 0 0 117 XLXL ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA TO DUT FIGURE 14-9: A Test Load Example RST EA# SST89E5xRDxA XTAL2 (NC) CLOCK XTAL1 SIGNAL V SS All other pins disconnected FIGURE 14-10: I Test Condition, DD Active Mode RST EA# SST89E5xRDxA XTAL2 (NC) CLOCK XTAL1 SIGNAL V SS All other pins disconnected FIGURE 14-11: I Test Condition, ...
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... SST89E5xRDxA 15.1 Valid Combinations Valid combinations for SST89E54RD2A SST89E54RD2A-40-C-NJE SST89E54RD2A-40-C-TQJE Valid combinations for SST89E58RD2A SST89E58RD2A-40-C-NJE SST89E58RD2A-40-C-TQJE Valid combinations for SST89E54RDA SST89E54RDA-40-C-PIE Valid combinations for SST89E58RDA SST89E58RDA-40-C-PIE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. © ...
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... FlashFlex MCU SST89E54RD2A/RDA / SST89E58RD2A/RDA 16.0 PACKAGING DIAGRAMS 40 1 Pin #1 Identifier .065 .075 Base Plane Seating Plane .015 Min. .063 .045 .090 .055 Note: 1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent. † = JEDEC min is .115; SST min is less stringent 2 ...
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... Removed WQFN/ QIF package information globally • Remove all I-grade part information globally Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2008 Silicon Storage Technology, Inc. SST89E54RD2A/RDA / SST89E58RD2A/RDA 34 33 10.00 ± 0.10 12.00 ± 0.25 23 ...