SST39WF1601-70-4C-MAQE-T Microchip Technology, SST39WF1601-70-4C-MAQE-T Datasheet - Page 4

• Manufacturer Part Number: SST39WF1601-70-4C-MAQE-T
• Description: 1.65V To 1.95V 16Mbit Multi-Purpose Flash 48 WFBGA 4x6x0.8 Mm T/R
• Manufacturer: Microchip Technology

Specifications of SST39WF1601-70-4C-MAQE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ
is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ
An additional Toggle Bit is available on DQ
used in conjunction with DQ
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ
pulse of Write operation. See Figure 8 for Toggle Bit timing
diagram and Figure 21 for a flowchart.
TABLE 1: Write Operation Status
Note: DQ
Data Protection
The SST39WF1601/1602 provide both hardware and soft-
ware features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V
inhibited when V
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadver-
tent writes during power-up or power-down.
©2011 Silicon Storage Technology, Inc.
Status
Normal
Operation
Erase-
Suspend
Mode
DD
6
2
will be set to “1” if a Read operation is attempted on an
) is valid after the rising edge of the last WE# (or CE#)
Power Up/Down Detection: The Write operation is
status information.
7
and DQ
6
Standard
Program
Standard
Erase
Read from
Erase-Suspended
Sector/Block
Read from
Non- Erase-Suspended
Sector/Block
Program
will toggle.
DD
2
require a valid address when reading
is less than 1.5V.
6
6
to check whether a particular
will produce alternating “1”s
DQ
DQ
DQ
Data
0
1
7
7
7
# Toggle No Toggle
# Toggle
Toggle
DQ
Data
2
1
, which can be
6
Toggle
Toggle
6
DQ
Data
T1.0 1297
N/A
bit will
2
6
)
4
Hardware Block Protection
The SST39WF1602 support top hardware block protec-
tion, which protects the top 32 KWord block of the device.
The SST39WF1601 support bottom hardware block pro-
tection, which protects the bottom 32 KWord block of the
device. The Boot Block address ranges are described in
Table 2. Program and Erase operations are prevented on
the 32 KWord when WP# is low. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase opera-
tions on that block.
TABLE 2: Boot Block Address Ranges
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of T
required after RST# is driven high before a valid Read can
take place (see Figure 16).
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39WF1601/1602 provide the JEDEC approved
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program opera-
tion requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table
6 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
device to read mode within T
can be V
mand sequence.
Product
Bottom Boot Block
Top Boot Block
SST39WF1601
SST39WF1602
16 Mbit Multi-Purpose Flash Plus
IL
or V
RP,
SST39WF1601 / SST39WF1602
IH
any in-progress operation will terminate and
, but no other value, during any SDP com-
RC.
The contents of DQ
0F8000H-0FFFFFH
000000H-007FFFH
Address Range
S71297-06-000
T2.0 1297
15
RHR
-DQ
01/11
is
8