SST39WF1601-70-4C-B3KE Microchip Technology, SST39WF1601-70-4C-B3KE Datasheet - Page 3

• Manufacturer Part Number: SST39WF1601-70-4C-B3KE
• Description: 1.65V To 1.95V 16Mbit Multi-Purpose Flash 48 TFBGA 6x8x1.2 Mm TRAY
• Manufacturer: Microchip Technology

Specifications of SST39WF1601-70-4C-B3KE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase Resume command (30H)
at any address in the last Byte sequence.
Chip-Erase Operation
The SST39WF1601/1602 provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 6 for the command sequence, Figure 10 for tim-
ing diagram, and Figure 24 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored. When WP# is low, any attempt to Chip-Erase will
be ignored. During the command sequence, WP# should
be statically held high or low.
©2011 Silicon Storage Technology, Inc.
2
toggling and DQ
6
at “1”. While in Erase-Suspend
3
Write Operation Status Detection
The SST39WF1601/1602 provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ
mode is enabled after the rising edge of WE#, which initi-
ates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data# Poll-
ing or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
Data# Polling (DQ
When the SST39WF1601/1602 are in the internal Pro-
gram operation, any attempt to read DQ
complement of the true data. Once the Program operation
is completed, DQ
though DQ
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase oper-
ation, any attempt to read DQ
internal Erase operation is completed, DQ
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 7 for
Data# Polling timing diagram and Figure 21 for a flowchart.
7
) and Toggle Bit (DQ
7
may have valid data immediately following the
7
will produce true data. Note that even
7
)
6
). The End-of-Write detection
7
will produce a ‘0’. Once the
7
or DQ
S71297-06-000
6
7
. In order to pre-
will produce the
7
will produce a
Data Sheet
01/11