SST25VF064C-80-4I-Q2AE-T Microchip Technology, SST25VF064C-80-4I-Q2AE-T Datasheet - Page 12

• Manufacturer Part Number: SST25VF064C-80-4I-Q2AE-T
• Description: 2.7V To 3.6V 64Mbit SPI Serial Flash 8 TDFN 6x8x0.8mm T/R
• Manufacturer: Microchip Technology

Specifications of SST25VF064C-80-4I-Q2AE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (8M x 8)
• Speed: 80MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-WDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
Fast-Read Dual I/O (50 MHz)
The Fast-Read Dual I/O (BBH) instruction reduces the total
number of input clock cycles, which results in faster data
access. The device is first selected by driving Chip Enable
CE# low. Fast-Read Dual I/O is initiated by executing an 8-
bit command (BBH) on SI/SIO
accepts address bits A23-A0 and a dummy byte on SI/
SIO
bits A23-A0 at a rate of two bits per clock. Odd address bits
A23 through A1 are input on SIO
A22 through A0 are input on SIO
the most significant bit is input first followed by A23/22, A21/
A20, and so on. Each bit is latched at the same rising edge
of the Serial Clock (SCK). The input data during the
dummy clocks is “don’t care”. However, the SIO
pin must be in high-impedance prior to the falling edge of
the first data output clock.
©2010 Silicon Storage Technology, Inc.
SIO 0
SIO 1
FIGURE 9: Fast-Read Dual I/O Sequence
SCK
CE#
0
and SO/SIO
MODE 3
MODE 0
1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
. It offers the capability to input address
BB
0
0
, alternately For example
, thereafter, the device
1
and even address bits
7 5 3 1 7 5 3 1
6 4 2 0 6 4 2 0 6 4 2 0
A23-16
0
and SIO
A15-8
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
7 5 3 1
1
A7-0
12
Following a dummy cycle, the Fast-Read Dual I/O instruc-
tion outputs the data starting from the specified address
location on the SIO
clock sequence, odd data bits D7, D5, D3, and D1; and
SIO
edge. CE# must remain active low for the duration of the
Fast-Read Dual I/O instruction cycle. The data output
stream is continuous through all addresses until terminated
by a low-to-high transition on CE#.
The internal address pointer will automatically increment
until the highest memory address is reached. Once the
highest memory address is reached, the address pointer
automatically increments to the beginning (wraparound) of
the address space. For example, once the data from
address location 7FFFFFH is read, the next output is from
address location 000000H. See Figure 9 for the Fast-Read
Dual I/o sequence.
0
Dummy
Cycle
outputs even data bits D6, D4, D2, and D0 per clock
X
X
64 Mbit SPI Serial Dual I/O Flash
7 5 3 1 7 5 3 1
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
MSB
DOUT
IO, Switches from Input to Output
N
1
MSB
and SIO
DOUT
N+1
7 5 3 1
MSB
0
DOUT
lines. SIO
N+2
SST25VF064C
S71392-04-000
MSB
7 5 3 1
DOUT
N+3
1
outputs, per
39
1392 F29.0
7
6
04/10