PIC18F96J65T-I/PF Microchip Technology, PIC18F96J65T-I/PF Datasheet - Page 4

• Manufacturer Part Number: PIC18F96J65T-I/PF
• Description: 96KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F96J65T-I/PF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F97J60 FAMILY
6. Module: Ethernet (RX Filter)
DS80433C-page 4
If a corrupted value was written due to an interrupt
occurring, perform the write again and reverify.
The source data must be stored in a non-problem
location.
The application should follow the following
procedure:
1. Copy the low byte to be written to the PHY into
2. Copy the high byte to be written to the PHY into
3. Move PRODL into MIWRL.
4. Wait one instruction cycle as required by the
5. Move PRODH into MIWRH.
6. Wait two T
7. Perform a PHY register read of the same
8. Compare the read result with the original value
Affected Silicon Revisions
When enabled, the Pattern Match receive filter
may allow some packets with an incorrect data
pattern to be received. Also, in certain configura-
tions, packets with a valid pattern may be
incorrectly discarded.
Work around
Do not use the Pattern Match hardware filter.
Instead, use the Unicast, Mutlicast, Broadcast and
Hash Table receive filters to accept all needed
packets and filter out unwanted ones in software.
Affected Silicon Revisions
A0
A0
X
X
the PRODL register.
PRODL is at address, FF3h, and not subject to
the memory address issue.
the PRODH register.
PRODH is at address, FF4h, and not subject to
the memory address issue.
MAC host interface logic.
(MISTAT<0>) until it is clear.
location.
copied to the PRODH:PRODL registers. If they
do not match, return to step 1.
A1
A1
X
X
A2
A2
X
X
CY
and then poll the BUSY bit
A3
A3
X
X
7. Module: Ethernet (TX)
When configured for half duplex and a transmit
operation encounters unusual collision timing,
there is a small chance that the Ethernet transmit
engine will internally deadlock. The PHY will stop
transmitting the packet and normal RX operations
will
(ECON1<3>) will stay set indefinitely. The TXIF
(EIR<3>) and TXERIF (EIR<1>) bits will not
become set.
This deadlock condition applies only to half-duplex
operation and is most readily observable when the
network has a duplex mismatch (i.e., PIC18F97J60
family device is configured for half duplex and the
remote node is configured for full duplex). In most
cases, high network utilization is needed to observe
the issue.
Work around
To prevent most transmit deadlock conditions,
issue a TX Logic Reset prior to transmitting each
packet:
1. Set TXRST (ECON1<7>).
2. Clear TXRST.
3. Wait 1.6 s or longer.
4. Set TXRTS to start the transmission.
Issuing a TX Logic Reset may cause the Ethernet
transmit error interrupt to occur and the associated
TXERIF bit to become set, which can be ignored.
To detect and recover from any possible deadlock
conditions, applications should implement a timer to
poll the TXRTS bit. If the Ethernet hardware enters
the deadlock state and fails to clear this bit by the
time the timer expires, software should manually
clear the TXRTS bit, issue a TX Logic Reset and
then set the TXRTS bit to retry transmission. The
timer should be cleared and restarted whenever the
application sets TXRTS. The timer expiration time
should be chosen to allow adequate time for
ordinary packets to finish transmitting, after
accounting for possible delays, due to the medium
being occupied by other nodes. For example, a
time-out value of 3 ms is suitable since it will allow a
maximum length 1518-byte packet to be transmit-
ted at 10Base-T speeds, while giving reasonable
margin to account for potential collisions.
Affected Silicon Revisions
A0
X
continue.
A1
X
A2
X
However,
 2010 Microchip Technology Inc.
A3
X
the
TXRTS
bit