PIC16LF1937-E/MV Microchip Technology, PIC16LF1937-E/MV Datasheet - Page 4

• Manufacturer Part Number: PIC16LF1937-E/MV
• Description: 14KB Flash, 512B RAM, 256B EEPROM, LCD, NanoWatt XLP 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1937-E/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC16F
• Core: PIC
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F1934/1936/1937 and PIC16LF1934/1936/1937
3.4 Capture mode Selected while CCPx Pin is
3.5 ECCPx Dead Time Delay in Half-Bridge mode
3.6 PWM with Pulse Steering
3.7 Capture mode Selected while CCPx Pin is
DS80479F-page 4
Held High
If the module is configured to capture on the first
rising edge and the CCPx pin is high at this time, a
capture will be triggered.
Work around
Clear the CCP interrupt flag (CCPxIF
immediately after configuring the module for a cap-
ture event.
Affected Silicon Revisions
In Half-Bridge mode the dead band delay is 1 T
longer than calculated for the first PWM cycle and
1.5 T
Work around
None.
Affected Silicon Revisions
Disabling a PWM output during a PWM cycle will
cause the output to end one T
expected.
Work around
None.
Affected Silicon Revisions
Held Low
If the module is configured to capture on the first
falling edge and the CCPx pin is low at this time, a
capture will be triggered.
Work around
Clear the CCP interrupt flag (CCPxIF
immediately after configuring the module for a cap-
ture event.
Affected Silicon Revisions
A2
A2
A2
A2
X
X
X
X
OSC
A3
A3
A3
A3
X
X
X
X
for following cycles.
A5
A5
A5
A5
X
X
X
X
A6
A6
A6
A6
X
X
X
X
OSC
time earlier than
=
=
OSC
0)
0)
4. Module: Brown-Out Reset (BOR)
4.1 Brown-Out Threshold
Configuring the BOR for 2.5V operation, the reset
will typically occur at 2.7V.
Work around
None.
Affected Silicon Revisions
A2
X
A3
A5
 2010 Microchip Technology Inc.
A6