XC6SLX16-2FTG256I Xilinx Inc, XC6SLX16-2FTG256I Datasheet - Page 19

• Manufacturer Part Number: XC6SLX16-2FTG256I
• Description: FPGA, SPARTAN-6 LX, 14K, 256FTGBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX16-2FTG256I

• No. Of Logic Blocks: 2278
• No. Of Macrocells: 14579
• Family Type: Spartan-6
• No. Of Speed Grades: 2
• Total Ram Bits: 589824
• No. Of I/o's: 186
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Package / Case: 256-BGA
• Mounting Type: Surface Mount
• Voltage - Supply: 1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 186
• Number Of Logic Elements/cells: 14579
• Package: 256FTBGA
• Family Name: Spartan®-6
• Device Logic Cells: 14579
• Device Logic Units: 9112
• Number Of Registers: 18224
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 186
• Ram Bits: 589824
• Core Supply Voltage Range: 1.14V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Production Silicon and ISE Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is
released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent
speed specification releases.
minimum corresponding supported speed specification version and ISE® software revisions. The ISE software and speed
specifications listed are the minimum releases required for production. All subsequent releases of software and speed
specifications are valid.
Table 27: Spartan-6 Device Production Software and Speed Specification Release
IOB Pad Input/Output/3-State Switching Characteristics
Table 28
input delay adjustments, output delays terminating at pads
(based on standard) and 3-state delays.
T
input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
T
pad through the output buffer of an IOB pad. The delay
varies depending on the capability of the SelectIO output
buffer.
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
3.
4.
5.
6.
XC6SLX4
XC6SLX9
XC6SLX16
XC6SLX25
XC6SLX25T
XC6SLX45
XC6SLX45T
XC6SLX75
XC6SLX75T
XC6SLX100
XC6SLX100T
XC6SLX150
XC6SLX150T
IOPI
IOOP
Blank entries indicate a device and/or speed grade in advance or preliminary status.
As marked with an N/A, LXT devices are not available with a -1L speed grade; LX4 devices are not available with a -3N speed grade.
Improved -3 specifications reflected in this data sheet require ISE 12.4 software with v1.15 speed specification.
Improved -2 specifications reflected in this data sheet require ISE 12.4 software and the 12.4 Speed Files Patch which contains the v1.17 speed
specification available on the
ISE 12.3 software with v1.12 speed specification is available using ISE 12.3 software and the 12.3 Speed Files Patch available on the
Center.
ISE 12.2 software with v1.11 speed specification is available using ISE 12.2 software and the 12.2 Speed Files Patch available on the
Center.
is described as the delay from IOB pad through the
is described as the delay from the O pin to the IOB
summarizes the values of standard-specific data
Device
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Table 27
lists the production released Spartan-6 family member, speed grade, and the
Center.
ISE 12.4 v1.15
ISE 12.1 v1.08
ISE 12.1 v1.08
ISE 12.1 v1.08
ISE 12.4 v1.15
-3
(3)
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
ISE 12.2 v1.11
ISE 12.2 v1.11
ISE 12.2 v1.11
ISE 12.2 v1.11
ISE 12.2 v1.11
ISE 12.2 v1.11
ISE 12.2 v1.11
ISE 12.2 v1.11
ISE 12.2 v1.11
ISE 12.2 v1.11
ISE 12.2 v1.11
ISE 12.4 v1.15
T
pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO
capability of the output buffer.
Table 29
described as the delay from the T pin to the IOB pad
through the output buffer of an IOB pad, when 3-state is
enabled (i.e., a high impedance state).
IOTP
Speed Grade Designations
N/A
-3N
is described as the delay from the T pin to the IOB
summarizes the value of T
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
ISE 12.3 v1.12
ISE 12.3 v1.12
ISE 11.5 v1.06
ISE 11.5 v1.07
ISE 12.1 v1.08
(1)
-2
(4)
(2)
(5)
(5)
IOTPHZ
ISE 13.1 v1.06
. T
IOTPHZ
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N/A
N/A
N/A
N/A
N/A
-1L
is
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