SI3210-GTR Silicon Laboratories Inc, SI3210-GTR Datasheet - Page 125

• Manufacturer Part Number: SI3210-GTR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3210-GTR

• Lead Free Status / RoHS Status: Compliant

5. Pin Descriptions: Si3210/11
Pin #
QFN
35
36
37
38
1
2
3
4
SDCH/DIO1
SDCL/DIO2
TSSOP
SRINGDC
Pin #
STIPDC
1
2
3
4
5
6
7
8
FSYNC
RESET
QGND
CAPM
CAPP
V
IREF
DTX
DDA1
SDCH/DIO1
10
11
12 13
1
2
3
4
5
6
7
8
9
FSYNC
RESET
Name
PCLK
DRX
DTX
38
INT
CS
14
37
15 16 17 18 19
QFN
36
35
34 33 32
Chip Select.
Active low. When inactive, SCLK and SDI are ignored and SDO is high
impedance. When active, the serial port is operational.
Interrupt.
Maskable interrupt output. Open drain output for wire-ORed operation.
PCM Bus Clock.
Clock input for PCM bus timing.
Receive PCM Data.
Input data from PCM bus.
Transmit PCM Data.
Output data to PCM bus.
Frame Synch.
8 kHz frame synchronization signal for the PCM bus. May be short or long
pulse format.
Reset.
Active low input. Hardware reset used to place all control registers in the
default state.
DC Monitor/General Purpose I/O.
DC-DC converter monitor input used to detect overcurrent situations in the
converter (Si3210 only). General purpose I/O (Si3211 only).
31
30
29
28
27
26
25
24
23
22
21
20
SDITHRU
DCDRV/DCSW
DCFF/DOUT
ITIPN
IRINGP
IGMP
TEST
GNDD
VDDD
ITIPP
V
IRINGN
DDA2
Rev. 1.45
SDCH/DIO1
SDCL/DIO2
SRINGDC
Description
SRINGE
STIPDC
FSYNC
RESET
SVBAT
QGND
CAPM
STIPE
CAPP
PCLK
V
IREF
DRX
DTX
DDA1
INT
CS
1
10
11
12
13
14
15
16
17
18
19
2
3
4
5
6
7
8
9
TSSOP
Si3210/Si3211
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
SCLK
SDO
SDITHRU
ITIPP
IRINGP
IRINGN
IGMP
IGMN
STIPAC
SDI
DCDRV/DCSW
DCFF/DOUT
TEST
GNDD
VDDD
ITIPN
V
GNDA
SRINGAC
DDA2
125