IDT82V1671AJ IDT, Integrated Device Technology Inc, IDT82V1671AJ Datasheet - Page 52

• Manufacturer Part Number: IDT82V1671AJ
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V1671AJ

• Number Of Channels: 4
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: PLCC
• Operating Temperature Classification: Industrial
• Pin Count: 28
• Mounting: Surface Mount
• Operating Current: 95mA
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Lead Free Status / RoHS Status: Compliant

4.1.2.2
the PCM highway. The number of the available time slots is determined
by the BCLK frequency. If the BCLK frequency is f kHz, the number of
the time slots that can be used is the result of f (kHz) divided by 64 kHz.
For example, if the frequency of BCLK is 512 kHz, then a total of eight
time slots are available. The CODEC accepts any BCLK signals ranging
from 256 kHz to 8.192 MHz at increment of 64 kHz.
of one channel occupies one time slot. The TT[6:0] bits in LREG1 select
the transmit time slot, while the RT[6:0] bits in LREG2 select the receive
time slot. The THS bit in LREG1 selects the transmit highway (DX1 or
DX2). The RHS bit in LREG2 selects the receive highway (DR1 or DR2).
data bits, while b15 and b14 are the same as the sign bit b13), one time
slot group consisting of two successive time slots are needed to contain
the voice data of one channel. The TT[6:0] bits in LREG1 select the
transmit time slot group. For example, if the TT[6:0] bits are set to
‘0000000’, it means that TS0 and TS1 are selected; if the TT[6:0] bits
are set to ‘0000001’, it means that TS2 and TS3 are selected. The
RT[6:0] bits in LREG2 select the receive time slot group in the same
way.
4.1.2.3
the selected edges of the BCLK. The transmit highway (DX1 or DX2) is
selected by the THS bit in LREG1. The frame sync signal (FSC)
identifies the beginning (Time Slot 0) of a transmit frame. The PCM data
is transmitted serially to DX1 or DX2 with MSB first.
highway on the selected edges of the BCLK. The receive highway (DR1
or DR2) is selected by the RHS bit in LREG2. The PCM data is received
serially from DR1 or DR2 with MSB first. The frame sync signal (FSC)
identifies the beginning (Time Slot 0) of a receive frame.
4.2
serial bus for interconnecting telecommunication ICs for a broad range
of applications − typically ISDN-based applications. The GCI bus
provides a symmetrical full-duplex communication link containing data,
control/programming and status channels. Providing data, control and
status information via a serial channel simplifies the line card layout and
reduces the cost.
follows:
downstream data via the DD pin. A complete GCI frame is sent
upstream and received downstream every 125 µs. The Frame Sync
signal (FSC) identifies the beginning of the transmit and receive frames
and all GCI time slots are referenced to it. The internal circuit of the
RSLIC & CODEC CHIPSET
The PCM data of each channel can be assigned to any time slot of
If the PCM data is A-law or µ-law compressed (8-bit), the voice data
For linear PCM data, which is a 16-bit 2's complement (b13 to b0 are
The PCM data of each channel is sent out to the PCM highway on
The General Circuit Interface (GCI) defines an industry-standard
The GCI interface consists of two data lines and two clock lines as
DU: Data Upstream carries data from the CODEC to the master
DD: Data Downstream carries data from the master processor to
FSC: Frame Synchronization signal (8 kHz) supplied to the CODEC
DCL: Data Clock signal (2.048 MHz or 4.096 MHz) supplied to the
The CODEC sends upstream data to the DU pin and receives
The PCM data from the master processor is received via the PCM
processor
the CODEC
CODEC
Time Slot Assignment
PCM Highway Selection
GCI INTERFACE
52
CODEC monitors the input DCL signal to determine which frequency
(2.048 MHz or 4.096 MHz) is being used. The internal timing will be
adjusted accordingly so that DU and DD operate at 2.048 MHz rate.
decoding. The L_CODE bit in GREG3 selects the data format:
4.2.1
slots. In each GCI time slot, the data upstream interface transmits four
8-bit bytes. They are:
different channels, named channel A and channel B. The compressed
voice data bytes for channel A and B are 8-bit wide:
from/to the master device for channel A and B;
with an MX bit and an MR bit. All real time signaling information is
carried on the C/I sub-byte. The MX (Monitor Transmit) bit and MR
(Monitor Receive) bit are used for handshaking functions for channel A
and B. Both MX and MR are active low.
data downstream interface logic controls the reception of data bytes
from the GCI bus. The two compressed voice data bytes of the GCI time
slot are transferred to the A-law or µ-law expansion logic circuit. The
expanded data is passed through the receive path of the signal
processor. The Monitor Channel and C/I Channel bytes are transferred
to the GCI control logic for process.
all four channels of the CODEC. The GCI time slot assignment is
determined by S1 and S0 pins as shown in
4.2.2
and each GCI time slot consists of four 8-bit bytes. Four of the eight GCI
time slots are used as the monitor channel and C/I channel. They have a
common data structure as follows:
from/to the master device for channel A and B.
with an MX bit and an MR bit. All real time signaling information is
carried on the C/I sub-byte. The MX (Monitor Transmit) bit and MR
(Monitor Receive) bit are used for handshaking functions for channel A
and B. Both MX and MR bits are active low.
data (a 16-bit 2’s complement number: b13 to b0 are data bits, while b15
and b14 are the same as the sign bit b13). Each GCI time slot consists
of four bytes: two bytes for the 16-bit linear voice data of channel A, the
other two bytes for the 16-bit linear data of channel B.
When S0 and S1 are both low, the linear GCI frame structure is as
shown in
The CODEC allows both compressed and linear data format coding/
L_CODE = 0:
L_CODE = 1:
In GCI compressed mode, one GCI frame consists of 8 GCI time
− Two voice data bytes from the A-law or µ-law compressor of two
− One monitor channel byte, containing the control data/coefficients
− One C/I channel byte, which contains a 6-bit C/I sub-byte together
The transmit logic controls the transmission of data onto the GCI bus.
The downstream data structure is the same as that of upstream. The
Figure - 31
In GCI compressed mode, two GCI time slots are required to access
In GCI linear mode, one GCI frame consists of eight GCI time slots
− Two Don’t Care bytes.
− One monitor channel byte, containing the control data/coefficients
− One C/I channel byte, which contains a 6-bit C/I sub-byte together
The other four GCI time slots are used to contain the linear voice
The GCI time slot assignment is determined by the S1 and S0 pins.
In linear operation, for one chip of the four-channel CODEC occupies
Figure - 32 on page
COMPRESSED GCI MODE
LINEAR GCI MODE
shows the structure of the overall compressed GCI frame.
Compressed code (default)
Linear code
IDT82V1671/IDT82V1671A, IDT82V1074
54.
Table -
19.