AM79Q02JC AMD (ADVANCED MICRO DEVICES), AM79Q02JC Datasheet
AM79Q02JC
Specifications of AM79Q02JC
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AM79Q02JC Summary of contents
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... Real Time Data register with interrupt (open drain or TTL output) Supports multiplexed SLIC inputs Broadcast state 256 kHz or 293 kHz chopper clock for AMD SLICs with switching regulator Maximum channel bandwidth for V.34 modems Advanced submicron CMOS technology makes the Am79Q02/021/031 QSLAC devices economical, with ...
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... PCM Highway Timing for (Transmit on Negative PCLK Edge PCM Highway Timing for (Transmit on Positive PCLK Edge Operating the QSLAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Channel Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SLIC Control and Data Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Clock Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 E1 Multiplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Debounce Filters Operation Real-Time Data Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Interrupt ...
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... Figure 6 Spurious Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7 A/A Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8 Clock Mode Option Figure 9 SLIC I/O, E1 Multiplex, and Real-Time Data Register Operation . . . . . . . . . . . 28 Figure 10 E1 Multiplex Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 11 MPI Real-Time Data Register or GCI Upstream SC Channel Data . . . . . . . . . . 30 Figure 12 QSLAC Device Block Diagram Figure 13 Robbed-Bit Frame ...
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... Channel 2 (CH 2) VOUT 2 VIN 3 Signal Processing Channel 3 (CH 3) VOUT 3 VIN4 Signal Processing Channel 4 (CH 4) VOUT 4 VREF SLIC CD1 1 CD2 CD1 2 CD2 SLIC C5 2 Interface CD1 (SLI) 3 CD2 CD1 4 CD2 CHCLK 4 Quad SLAC Device Time Slot Assigner Clock & Reference Circuits Microprocessor Interface ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79Q02/021/031 DEVICE NUMBER/DESCRIPTION Am79Q02/021/031 Quad Subscriber Line Audio-Processing Circuit (QSLAC) Device ...
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... Am79Q021JC AGND 13 VIN 14 3 VOUT 15 3 VIN 16 4 VOUT Notes: 1. Pin 1 is marked for orientation. 2. RSVD = Reserved pin; should not be connected externally to any signal or supply. 6 44-Pin PLCC Am79Q02JC VIN DCLK VOUT 2 37 DIO VIN 2 36 TSCA VCCA 35 DGND VREF 34 PCLK AGND ...
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CONNECTION DIAGRAM (TQFP PACKAGE) Top View VOUT 1 VIN 1 VOUT 2 VIN 2 VCCA VREF AGND VIN 3 VOUT 3 VIN 4 VOUT 4 Notes: 1. Pin 1 is marked for orientation. 2. RSVD = Reserved pin; should not ...
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... Inputs/Outputs Control. C3, C4, and C5 are TTL-compatible programmable Input or Output (I/O) ports. They –C4 can be used to monitor or control the state of SLIC or any other device associated with sub –C5 scriber line interface. The direction, input or output, is programmed using MPI Command 22 outputs, C3, C4, and C5 can be used to control relays, illuminate LEDs, or perform any other function requiring a latched TTL compatible signal for control ...
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... Master Clock (Input)/Enable CD1 Multiplex (Output). The Master Clock can be a 1.536 MHz, 1.544 MHz, or 2.048 MHz (times clock for use by the digital signal processor. If the internal clock is derived from the PCM Clock Input (PCLK), this pin can be used out- put to control AMD SLICs having multiplexed hookswitch and ground-key detector outputs. PCLK Input PCM Clock ...
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Pin Names Type VOUT – Outputs Analog. The received digital data at DRA or DRB is processed and converted to an analog 1 VOUT signal at the VOUT pin. VOUT 4 2, VOUT voltages are referenced to VREF. VREF Output ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . –60°C < T Ambient Operating Temperature –40°C < T Ambient Relative Humidity . . . . . . . . . . . . 5% to 95% ...
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ELECTRICAL CHARACTERISTICS Typical values are for and nominal supply voltages. Minimum and maximum values are over the A temperature and supply voltage ranges shown in Operating Ranges. Symbol Parameter Descriptions V Input Low voltage IL V ...
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Transmission Characteristics Table 1. 0 dBm0 Voltage Definitions with Unity Gain GX, GR, AX, and AR Signal at Digital Interface A-law digital mW or equivalent (0 dBm0) -law digital mW or equivalent (0 dBm0) ±22,827 peak linear ...
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Attenuation Distortion 2 Attenuation (dB) 1 0.125 0 Transmit only – 0.125 200 300 Group Delay Distortion For either transmission path, the group delay distortion is within the limits shown in Figure 2. The minimum value of the group delay ...
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Variation of Gain with Input Level The gain deviation relative to the gain at –10 dBm0 is within the limits shown in Figure 3 for either transmission path when the input is a sine wave signal of frequency 1014 Hz. ...
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Total Distortion, Including Quantizing Distortion The signal-to-total distortion will exceed the limits shown in Figure 4 for either transmission path when the input is a sine wave signal of frequency 1014 Hz –45 Figure 4. A-law/ ...
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Discrimination against Out-of-Band Input Signals When an out-of-band sine wave signal with frequency and level A is applied to the analog input, there may be frequency components below 4 kHz at the digital output which are caused by the out-of-band ...
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Discrimination against 12- and 16-kHz Metering Signals If the QSLAC device is used in a metering application where 12-kHz or 16-kHz tone bursts are injected onto the telephone line toward the subscriber, a portion of those tones may also appear ...
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Overload Compression Figure 7 shows the acceptable region of operation for input signal levels above the reference input power (0 dBm0). The conditions for this figure are: (1) 1.2 dB < PCM input; and (4) measurement analog-to-analog. 9 ...
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... Chip select off time, Input state (Note 1) ICSO 10 t Input data setup time IDS 11 t Input data hold time IDH 12 t SLIC output latch valid OLH 13 t Chip select setup time, Output state OCSS 14 t Chip select hold time, Output state OCSH 15 t ...
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Master Clock No. Symbol 37 A Master clock accuracy MCY 38 t Rise time of clock MCR 39 t Fall time of clock MCF 40 t MCLK High pulse width MCH 41 t MCLK Low pulse width MCL Auxiliary Output ...
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Microprocessor Interface (Input Mode DCLK Data D I/O Valid Outputs C5–C1 Microprocessor Interface (Output Mode DCLK Three-State Data OH ...
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PCM Highway Timing for (Transmit on Negative PCLK Edge PCLK TSCA/ TSCB 32 DXA/DXB DRA/DRB Time Slot Zero Clock Slot Zero ...
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PCM Highway Timing for (Transmit on Positive PCLK Edge PCLK TSCA/ TSCB DXA/DXB DRA/DRB 24 Time Slot Zero Clock Slot Zero ...
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... minimizing the impact to existing system software. SLIC Control and Data Lines The QSLAC device has up to five SLIC digital interface pins per channel (CD1–C5). Each of these pins can be programmed as either an input or an output using the I/O Direction register (Commands 22 and 23) (see Figure 9) ...
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... It also shows the operation of the Real Time Register. The QSLAC device E1 output signal connects directly to the E1 inputs of all four connected SLICs and is used by those SLICs to select an internal comparator to route to the SLIC’s DET output. This E1 signal is also used internally by the QSLAC device for controlling the multiplex operation and timing ...
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... The LD Enable pulse allows CD1 pin data to be routed through the CD1 latch. The uncertain states of the SLIC’s DET output, and the masked times where that DET data is ignored are shown in this timing diagram. Using this isolation of masked times, the CD1 ...
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... MCLK/E1 for details E1P INT Note: * Transparent latches: When enable input is high, Q output follows D input. When enable input goes low, Q output is latched at last state. Figure 9. SLIC I/O, E1 Multiplex and Real-Time Data Register Operation 28 SLIC I/O Register MPI Command 20, — — CD1B C5 D ...
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... CDB bit of the Real Time Data Register. Each channel has its own filter, and each filter’s time can be individually programmed. The input to the filter comes from either the CD2 bit of the SLIC I/O Data Register (Command 20 and 21, 52/53h), when E1 Pulse Period 203.125 s 4 ...
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CD1 kHz) Notes: * Transparent latch: Output follows input when EN is high; output holds last state when EN is low Debounce Counter: Output goes high after counting to programmed (DSH) number of 1 ...
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... Chopper Clock On the Am79Q02JC there is a chopper clock output to drive the switching regulator on some AMD SLICs. The clock frequency is selectable as 256 or 292.57 kHz by the CHP bit (Command 12). The chopper output must be turned on with the ECH bit (Command 45) ...
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Transmit time slots and receive time slots are set and 3 for channels and 4, respectively. The clock slots are set to 0, with transmit on the negative edge. 8. DXA port ...
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... Two-Wire Impedance Matching Two feedback paths on the QSLAC device synthesize the two-wire input impedance of the SLIC by providing a programmable feedback path from VIN to VOUT. The Analog Impedance Scaling Network (AISN programmable analog gain of –0.9375 to +0.9375 from VIN to VOUT . The Z filter is a programmable digital ...
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... G is the SLIC echo gain into an open circuit, 440 G is the SLIC echo gain into a short circuit, and ZSL 44 is the SLIC input impedance without the QSLAC device. The gain can be varied from –0.9375 to +0.9375 in 31 steps of 0.0625. The AISN gain is determined by the ...
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During this test, the VIN input is ignored and the VOUT output is connected to VREF. Speech Coding The A/D and D/A conversion follows either the A-law µ ...
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... R) are not optimized. The balance filter was de- signed to give acceptable balance into a variety of im- pedances. The nominal input impedance was set to 815 . If the SLIC circuit differs significantly from this design, the default filters cannot be used and must be replaced by programmed coefficients. ...
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Commands are provided to assign values to the following global chip parameters: Transmit PCM Clock Edge Interrupt Output Drive state Chopper Clock Frequency Select Signaling on the PCM Highway Select Master Clock Frequency Channel Enable register Debounce Time for CD1 ...
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... Read Real Time Data Register 4F Read Real Time Data Register and Clear Interrupt 50/51 Write/Read AISN and Analog Gains 52/53 Write/Read SLIC Input/Output Register 54,55 Write/Read SLIC Input/Output Direction and Status Bits 60/61 Write/Read Operating Functions 6C/6D Write/Read Interrupt Mask Register 70/71 Write/Read Operating Conditions 73 ...
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... The PCM inputs are disabled and the PCM outputs are high impedance unless signaling on the PCM highway is programmed (SMODE = 1). The analog output (VOUT) is disabled and biased at 2.1 V. The channel status (CS) bit in the SLIC I/O Direction and Channel Status Register is set Software Reset ...
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No Operation (06h) Command 5. Activate Channel (Operational Mode) (0Eh) Command This command places the device in the Active mode and sets CSTAT = 1. No valid PCM data is transmitted until after the second FS pulse is received ...
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Write/Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge (44/45h) R Write R Read Command I/O Data Transmit on A and B TAB = 0* TAB = 1 Transmit Edge XE = ...
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Master Clock Frequency CSEL = 0000 CSEL = 0001 CSEL = 0010 CSEL = 0011 CSEL = 01xx CSEL = 10xx CSEL = 11xx CSEL = 1010* These commands do not depend on the state of the Channel Enable Register. ...
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Read Real-Time Data Register (4D/4Fh not clear interrupt Clear interrupt This register writes/reads real-time data with or without clearing the interrupt. Command Output Data Real Time Data CDA1 CDB1 CDA2 CDB2 ...
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... Pins CD1, CD2, and C3 through C5 are set The data appears latched on the CD1, CD2, and C3 through C5 SLIC I/O pins, provided they were set in the Output mode (see Command 22). The data sent to any of the pins set to the Input mode is latched, but does not appear at the pins ...
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Write/Read Operating Functions (60/61h) R Write R Read Command I/O Data Linear Code C C A-law or µ-law A/µ A/µ Filter EGR = 0* EGR ...
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Write/Read Interrupt Mask Register (6C/6Dh) R Write R Read Command I/O Data Mask CD Interrupt MCDxy = 0 MCDxy = Masked: A change does not cause the Interrupt Pin to go ...
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Read Revision Code Number (RCN) (73h) Command I/O Data This command returns an 8-bit number (RCN) describing the revision number of the QSLAC device. This command does not depend on the state of the Channel Enable Register. 31, 32. ...
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Write/Read Z Filter Coefficients (FIR and IIR) (84/85h) R Write R Read This command writes and reads both the FIR and IIR filter sections simultaneously. Command I/O Data Byte 1 I/O Data Byte 2 ...
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Write/Read B1 Filter Coefficients (86/87h) R Write R Read Command I/O Input Data Byte 1 I/O Input Data Byte 2 I/O Input Data Byte 3 I/O Input Data Byte 4 I/O Input Data Byte ...
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Write/Read X Filter Coefficients (88/89h) R Write R Read Command I/O Input Data Byte 1 I/O Input Data Byte 2 I/O Input Data Byte 3 I/O Input Data Byte 4 I/O Input Data Byte ...
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Write/Read R Filter Coefficients (8A/8Bh) R Write R Read Command I/O Input Data Byte 1 I/O Input Data Byte 2 I/O Input Data Byte 3 I/O Input Data Byte 4 I/O Input Data Byte ...
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Write/Read B2 Filter Coefficients (IIR) (96/97h) R Write R Read Command I/O Data Byte 1 I/O Data Byte 2 This function is described in Write/Read B1 Filter Coefficients (FIR) on page 49. Power Up ...
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Read Transmit PCM Data (CDh) Command Output Data Byte 1 Output Data Byte 2 RSVD Reserved for future use. Always write as 0, but 0 is not guaranteed when read. Upper Transmit Data XDAT contains A-law or -law transmit ...
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The IIR filter output is then multiplied normalize the overall gain coefficients, but it also includes the initial 1/Z and normalization, is actually Z 50, 51. Write/Read ...
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Write/Read Ground Key Filter (E8/E9h) R Write R Read Command I/O Data Filter Ground Key GK = 0–15 GK contains the filter sampling time (in ms) of the CD1B data (usually Ground Key) or ...
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PROGRAMMABLE FILTERS General Description of CSD Coefficients The filter functions are performed by a series of multiplications and accumulations. A multiplication occurs by repeatedly shifting the multiplicand and summing the result with the previous value at that summation node. The ...
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In the QSLAC device, a coefficient, h coefficients, each being made bits and formatted as Cxy mxy, where Cxy is 1 bit (MSB) and mxy is 3 bits. Each CSD coefficient is broken down as follows: Cxy ...
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A-Law and -Law Companding Table 2 and Table 3 show the companding definitions used for A-law and -law PCM encoding Intervals Segment x Interval Segment Number Size End Points 128 ...
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Intervals Value at Segment x Interval Segment Number Size End Points 256 128 ...
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... R) were not optimized. The balance filter was designed to give acceptable balance into a variety of impedances. The nominal input impedance was set to 815 . If the SLIC circuit differs significantly from this design, the default filters cannot be used and must be replaced by programmed coefficients. ...
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PHYSICAL DIMENSIONS PL032 .485 .495 .447 .453 .585 Pin 1 I.D. .595 .547 .553 .026 .032 TOP VIEW PL044 .685 .695 .650 .656 Pin 1 I.D. .685 .695 .650 .656 .026 .050 REF .032 TOP VIEW .009 .015 .125 .140 ...
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PQT044 44 1 9.80 10.20 11.80 12.20 0.95 1.05 0.80 BSC 0.30 0.45 1.00 REF. 62 11.80 12.20 9.80 10.20 11 – 13 1.20 MAX 16-038-PQT-2 11 – 13 PQT 44 7-11-95 ae Am79Q02/021/031 Data Sheet ...
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REVISION SUMMARY Revision B to Revision C • In the Connection Diagrams section, “INT” was changed to “INT” for Am79Q021JC and Am79Q021VC. • “Frame sync” information was added to the first paragraph on page 31. Revision C to Revision D ...
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The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to ...