PEB4265TV1.2T Infineon Technologies, PEB4265TV1.2T Datasheet - Page 112

• Manufacturer Part Number: PEB4265TV1.2T
• Manufacturer: Infineon Technologies

Specifications of PEB4265TV1.2T

• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 22
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary
4.8.2.5
The path of the DC levelmeter is shown in
will be determined and prepared depending on certain configuration settings. The
selected input signal becomes digitized after pre-filtering and analog-to-digital
conversion. The DC levelmeter is selected and enabled as shown in
Table 28
LM-SEL[3:0] in
register LMCR2
0100
0101
1001
1010
1011
1101
1110
1111
The effective sampling rate after the decimation stages is 2 kHz. The decimated value
has a resolution of 19 bits. The offset compensation value (see
the offset registers OFR1 (bits OFFSET-H[7:0]) and OFR2 (bits OFFSET-L[7:0]) can be
set to eliminate the offset caused by the SLIC-E/-E2/-P current sensor, pre-filter, and
analog-to-digital converter. After the summation point the signal passes a programmable
digital gain filter. The additional gain factor is either 1 or 16 depending on register LMCR1
(bit DC-AD16):
– LMCR1 (bit DC-AD16) = 0: No additional gain factor
– LMCR1 (bit DC-AD16) = 1: Additional gain factor of 16
The rectifier after the gain filter can be turned on/off with:
– LMCR2 (bit LM-RECT) = 0: Rectifier disabled
– LMCR2 (bit LM-RECT) = 1: Rectifier enabled
A shift-factor K
integration operation to create an overflow. If an overflow in the levelmeter occurs, the
output result will be ± fullscale (see Table 27).
If the shift factor K
the integration result divided by 8.
The shift factor K
Data Sheet
DC Levelmeter
Selecting DC Levelmeter Path
INTDC
INTDC
INTDC
DC Levelmeter Path
DC out voltage on DCP-DCN
DC current on IT
DC current on IL
Voltage on IO3
Voltage on IO4
V
Offset of DC-pre-filter (short circuit on DC-pre-filter input)
Voltage on IO4 – IO3
in front of the integrator prevents the levelmeter during an
is set in the CRAM (offset address 0x76):
DD
is set to e.g. 1/8, the content of the levelmeter result register is
112
Figure
45. Hereby, the DC levelmeter results
Operational Description
Chapter
Table
4.8.2.8) within
28:
2000-07-14
DuSLIC