DJLXT972ALC.A4 Cortina Systems Inc, DJLXT972ALC.A4 Datasheet - Page 59

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DJLXT972ALC.A4

Manufacturer Part Number
DJLXT972ALC.A4
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of DJLXT972ALC.A4

Lead Free Status / RoHS Status
Not Compliant
LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
Figure 27
Figure 28
Table 34
Cortina Systems
Auto-Negotiation and Fast Link Pulse Timing
Fast Link Pulse Timing
Auto-Negotiation and Fast Link Pulse Timing Parameters
®
Clock/Data pulse width
Clock pulse to Data pulse
Clock pulse to Clock pulse
FLP burst width
FLP burst to FLP burst
Clock/Data pulses per burst
1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
LXT972A Single-Port 10/100 Mbps PHY Transceiver
testing.
TPOP
TPOP
Parameter
Clock Pulse
FLP Burst
t1
t4
Symbol
t2
t1
t2
t3
t4
t5
55.5
Min
123
17
t5
8
Data Pulse
Typ
100
t1
t3
12
2
1
Max
63.8
127
24
33
FLP Burst
7.2 AC Timing Diagrams and
pulse or data
Each clock
Units
pulse
Clock Pulse
ms
ms
ns
μ s
μ s
B3465-01
B3464-01
Conditions
Parameters
Test
Page 59

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