L-FW322-06-T100-DB LSI, L-FW322-06-T100-DB Datasheet - Page 16

• Manufacturer Part Number: L-FW322-06-T100-DB
• Manufacturer: LSI

Specifications of L-FW322-06-T100-DB

• Lead Free Status / RoHS Status: Compliant

FW322 06 T100
1394A PCI PHY/Link Open Host Controller
Pin Information
Table 1. Pin Descriptions (continued)
* Active-low signals within this document are indicated by an N following the symbol names.
Note: For those applications when one or more FW322 ports are not wired to a connector, those unused ports may be left unconnected without
16
16
100
Pin
99
93
94
95
96
97
98
normal termination. When a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state.
Symbol*
RESETN
PTEST
V
V
XO
SM
SE
XI
DD
SS
(continued)
Analog I/O
Type
—
—
I
I
I
I
Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel
resonant fundamental mode crystal. Although when a 24.576 MHz
clock source is used, it can be connected to XI with XO left uncon-
nected. The optimum values for the external shunt capacitors are
dependent on the specifications of the crystal used. It is necessary to
add an external series resistor to the XO pin. The value of the resistor
is nominally 400 Ω. Note that it is very important to place the crystal
as close as possible to the XO and XI pins, i.e., within 0.5 in./
1.27 cm. For more important details regarding the crystal, refer to the
FW323/FW322 Hardware Implementation Design Guideline Applica-
tion Note.
Reset (Active-Low). When RESETN is asserted low (active), a 1394
bus reset condition is set on the active cable ports and the FW322 is
reset to the reset start state. To guarantee that the PHY will reset, this
pin must be held low for at least 2 ms. An internal pull-up resistor,
connected to V
(0.1 µF) and resistor (510 kΩ), in parallel, are required to connect this
pin to ground. This circuitry will ensure that the capacitor will be
discharged when PHY power is removed. The input is a standard
logic buffer and can also be driven by an open-drain logic output
buffer. Do not leave this pin unconnected. This pin is also used with
the EEPROM interface. It is the powerup reset pin. This pin is
asserted low (active) to indicate a powerup reset. Refer to the
FW322 06/FW323 06 EEPROM Interface and Start-up Behavior
Application Note sections titled Initiation of EEPROM Load and Initial
Powerup.
Test. Used by Agere for device manufacturing testing. Tie to V
normal operation.
Test Mode Control. SM is used during Agere’s manufacturing test
and should be tied to V
Test Mode Control. SE is used during Agere’s manufacturing test
and should be tied to V
Digital Power.
Digital Ground.
DD
, is provided, so only an external delay capacitor
SS
SS
for normal operation.
for normal operation.
Description
December 2004
Agere Systems Inc.
Product Brief
SS
for