1893Y-10 IDT, Integrated Device Technology Inc, 1893Y-10 Datasheet - Page 35

• Manufacturer Part Number: 1893Y-10
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 1893Y-10

• Lead Free Status / RoHS Status: Not Compliant

6.8 Status Interface
ICS1893 Rev C 6/6/00
The ICS1893 LSTA pin provides a Link Status, and its LOCK pin provides a Stream Cipher Locking Status.
In addition, as listed in
results of continual link monitoring by providing signals that are intended for driving LEDs. (For the pin
numbers, see
Table 6-3.
Note:
1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input
2. A software reset does not affect the state of a multi-function configuration pin. During a software reset,
3. Each multi-function configuration pin must be pulled either up or down with a resistor to establish the
4. As outputs, the asserted state of a multi-function configuration pin is the inverse of the sense sampled
5. Adding 10K
6. PHY address 00 tri-states the MII interface. (Do not select PHY address 00 unless you want the MII
P0AC
P1CL
P2LI
P3TD
P4RD
ICS1893 - Release
that is sampled when the ICS1893 exits the reset state. After sampling is complete, these pins are
output pins that can drive status LEDs.
all multi-function configuration pins are outputs.
address of the ICS1893. LEDs may be placed in series with these resistors to provide a designated
status indicator as described in Table 6-3.
Caution:
during reset. This inversion provides a signal that can illuminate an LED during an asserted state. For
example, if a multi-function configuration pin is pulled down to ground through an LED and a
current-limiting resistor, then the sampled sense of the input is low. To illuminate this LED for the
asserted state, the output is driven high.
power-ramp conditions.
tri-stated.)
Pin
Pins for Monitoring the Data Link
AC (Link Activity) LED
CL (Collisions) LED
LI (Link Integrity) LED
TD (Transmit Data) LED
RD (Receive Data) LED
Table
LED Driven by the Pin’ s Output Signal
All pins listed in Table 6-3 must not float.
resistors across the LEDs ensures the PHY address is fully defined during slow VDD
9.3.2.)
Table
6-3, the ICS1893 provides five multi-function configuration pins that report the
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
35
Chapter 6 Interface Overviews
June, 2000