USB3250-ABZJ Standard Microsystems (SMSC), USB3250-ABZJ Datasheet - Page 3

• Manufacturer Part Number: USB3250-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of USB3250-ABZJ

• Lead Free Status / RoHS Status: Compliant

Hi-Speed USB Device Transceiver with UTMI Interface
General Description
Block Diagram
SMSC USB3250
The USB3250 provides the Physical Layer (PHY) interface to a USB 2.0 Device Controller. The IC is
available in a 56 pin QFN.
The USB3250 is a USB 2.0 physical layer transceiver (PHY) integrated circuit. SMSC's proprietary
technology results in low power dissipation, which is ideal for building a bus powered USB 2.0
peripheral. The PHY can be configured for either an 8-bit unidirectional or a 16-bit bidirectional parallel
interface, which complies with the USB Transceiver Macrocell Interface (UTMI) specification. It
supports 480Mbps transfer rate, while remaining backward compatible with USB 1.1 legacy protocol
at 12Mbps.
All required termination for the USB 2.0 Transceiver is internal. Internal 5.25V short circuit protection
of DP and DM lines is provided for USB compliance.
While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs
needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming
data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding.
TXVALID
RESET
SUSPENDN
XCVRSELECT
TERMSELECT
LINESTATE[1:0]
CLKOUT
DATABUS16_8
Figure 1 USB3250 Functional Block Diagram
CONTROL
PWR
PRODUCT PREVIEW
Conversion
Conversion
Bit Unstuff
LOGIC
Parallel to
RX State
LOGIC
Machine
Decode
TX State
Serial to
Bandgap Voltage Reference
Machine
Bit Stuff
Parallel
Encode
NRZI
Serial
NRZ
RX
TX
Current Reference
BIASING
Recovery Unit
3
Recovery
HS_DRIVE_ENABLE
Elasticity
Clock
HS_CS_ENABLE
Data
Buffer
Clock
and
XTAL OSC
PLL and
HS_DATA
RPU_EN
VP
VM
VPO
VMO
OEB
1.5k Ω
FS
TX
HS
TX
SE+
SE-
RX
FS
RX
HS
RX
HS
SQ
TX
FS
FS
Clocking
System
DP
DM
Revision 1.7 (05-11-07)