SI3011-F-FSR Silicon Laboratories Inc, SI3011-F-FSR Datasheet
SI3011-F-FSR
Specifications of SI3011-F-FSR
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SI3011-F-FSR Summary of contents
Page 1
... The Voice DAA is available in one 20-pin TSSOP (Si3050) and one 16-pin TSSOP/SOIC (Si3011) and requires minimal external components. The Si3050 interfaces directly to standard telephony PCM interfaces. ...
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... Si3050 + Si3011 2 Rev. 1.11 ...
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... Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.28. Transhybrid Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.29. Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.30. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.31. Communication Interface Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.32. PCM Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.33. Companding in PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.34. 16 kHz Sampling Operation in PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.35. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.36. GCI Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Si3050 + Si3011 Rev. 1.11 Page 3 ...
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... Receive SC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.46. Transmit SC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Appendix—IEC/UL60950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7. Pin Descriptions: Si3050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 8. Pin Descriptions: Si3011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 10. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11. Package Outline: 20-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13. Package Outline: 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Silicon Labs Si3050 Support Documentation ...
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... The Si3050 specifications are guaranteed when the typical application circuit (including component tolerance) and any Si3050 and any Si3011 are used. See "2. Typical Application Schematic" on page 17 for the typical application circuit. 2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. ...
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... Si3050 + Si3011 Table 2. Loop Characteristics = = (V 3 °C for K-Grade, see Figure 1 on page Parameter Symbol DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage On-Hook Leakage Current Operating Loop Current Operating Loop Current DC Ring Current * Ring Detect Voltage Ring Frequency Ringer Equivalence Number *Note: The ring signal is guaranteed to not be detected below the minimum ...
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... Test Condition – pin PDN = 1, PDL = PDN = 1, PDL = 1 D Rev. 1.11 Si3050 + Si3011 Min Typ Max Unit 2.0 — — V — — 0.8 V 2.4 — — V — — 0.35 V 2.4 — — V — — 0.35 V –10 — 10 µA — 8 — 5.0 6 ...
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... Si3050 + Si3011 Table 4. AC Characteristics = = (V 3 °C for F/K-Grade Parameter Sample Rate PCLK Input Frequency Receive Frequency Response Receive Frequency Response 1 Transmit Full-Scale Level 1,3 Receive Full-Scale Level 4,5,6 Dynamic Range Receive Total Harmonic 6,7 Distortion Receive Total Harmonic 6,7 ...
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... Note: Permanent device damage can occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods might affect device reliability. Si3050 + Si3011 Symbol Value V – ...
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... Si3050 + Si3011 Table 6. Switching Characteristics—General Inputs = = (V 3 °C for K-Grade Parameter Cycle Time, PCLK PCLK Duty Cycle PCLK Jitter Tolerance Rise Time, PCLK Fall Time, PCLK 2 PCLK Before RESET 3 RESET Pulse Width CS, SCLK Before RESET Rise Time, Reset Notes: 1 ...
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... SDI t d1 SDO = 20 pF) L Test Symbol Conditions su1 su2 su2 Figure 3. SPI Timing Diagram Rev. 1.11 Si3050 + Si3011 Min Typ Max Unit 61.03 — — ns — — — — — — — — — — — — — — — — — ...
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... Si3050 + Si3011 Table 8. Switching Characteristics—PCM Highway Serial Interface = = (V 3 °C for K-Grade Parameter Cycle Time PCLK Valid PCLK Inputs 2 FSYNC Period PCLK Duty Cycle PCLK Jitter-Tolerance FSYNC Jitter Tolerance Rise Time, PCLK Fall Time, PCLK Delay Time, PCLK Rise to DTX Active ...
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... Rev. 1.11 Si3050 + Si3011 Min Typ Max Units — 488 — ns — 244 — ns — 2.048 — MHz — 4.096 — MHz — 125 — µ — — — — ±120 ns — — — ...
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... Si3050 + Si3011 PCLK FSYNC DRX DTX Figure 6. GCI Highway Interface Timing Diagram (2x PCLK Mode) Table 10. Digital FIR Filter Characteristics—Transmit and Receive = = (V 3.0 to 3.6 V, Sample Rate 8 kHz Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay Note: Typical FIR filter characteristics for Fs Table 11. Digital IIR Filter Characteristics— ...
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... Figure 8. FIR Receive Filter Passband Ripple For Figures 7–10, all filter plots apply to a sample rate kHz. For Figures 11–14, all filter plots apply to a sample rate kHz. Si3050 + Si3011 Figure 9. FIR Transmit Filter Response Figure 10. FIR Transmit Filter Passband Ripple Rev. 1.11 15 ...
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... Si3050 + Si3011 Figure 11. IIR Receive Filter Response Figure 12. IIR Receive Filter Passband Ripple Figure 13. IIR Transmit Filter Response 16 Figure 14. IIR Transmit Filter Passband Ripple Figure 15. IIR Receive Group Delay Figure 16. IIR Transmit Group Delay Rev. 1.11 ...
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... Typical Application Schematic Si3050 + Si3011 Rev. 1.11 17 ...
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... Si3050 + Si3011 3. Bill of Materials Component C1 C5, C6, C50, C51 C7 C8, C9 C10 1 C30, C31 2 D1, D2 Dual Diode, 225 mA, 300 V, (CMPD2004S) FB1, FB2 Q1 Q4, Q5 RV1 R5 R7 R10 R11 3 R12, R13 4 R15, R16 1 R30, R32 1 R31, R33 R51, R52, R53 Notes: 1. R7–R8 may be substituted for R30–R33 and C30–C31 for lower cost, but reduced CID performance. ...
Page 19
... The PWMM[1:0] bits (Register 1, bits 5:4) select one of three different PWM output modes for the AOUT signal, including a delta-sigma data stream kHz return to 0 PWM output, and a balanced 32 kHz PWM output. R41 C41 Value NPN KSP13 Venkel, SMEC 150 1/10 W, ±5% Venkel, SMEC, Panasonic Rev. 1.11 Si3050 + Si3011 LS1 Q6 Supplier Intervox Fairchild 19 ...
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... The communications link is disabled by default. To enable it, the PDL bit (Register 6, bit 4) must be cleared. No communication between the Si3050 and Si3011 can occur until this bit is cleared. Allow the PLL to lock to the PCLK and FSYNC input signals before clearing the PDL bit. 5.5. Power Management The Si3050 supports four basic power management operation modes ...
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... DRX and receive that digital test pattern back on DTX. To enable this mode, set the IDL bit (Register 1, bit 1). The communications link is tested in this mode. The digital stream is delivered across the isolation capacitors, C1 and C2, of the "2. Typical Application Rev. 1.11 Si3050 + Si3011 ability to determine system side is established ...
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... Communication with the line-side device takes less than establish. 5.9. Revision Identification The Si3050 provides information to determine the revision of the Si3050 and/or the Si3011. The REVA[3:0] bits (Register 11) identify the revision of the Si3050, where 0101b denotes revision E. The REVB[3:0] bits (Register 13) identify the revision of the line-side device, where 0110b denotes revision F ...
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... the LVS register displays all 0s. 36.3 39.6 42.9 46.2 49.5 52.8 56.1 59.1 62.7 66 69.3 72.6 75.9 79.2 Loop Current (mA) Rev. 1.11 Si3050 + Si3011 below. This register may display Possible Overload 82.5 85.8 89.1 92.4 95.7 99 102.3 ...
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... DAA. Below this threshold, the reported value of loop current is unpredictable. The minimum operating loop current of the Si3050+Si3011 chipset is 10 mA. When the LCS bits reach max value, the Loop Current Sense Overload Interrupt bit (Register 4) fires. LCSOI firing however, does not necessarily imply that an overcurrent situation has occurred ...
Page 25
... Only the magnitude of the measured value is used for comparison to the threshold programmed into the CVT[7:0] bits. Therefore, only positive numbers should be used as a threshold. Rev. 1.11 Si3050 + Si3011 selected by the CVS bit 25 ...
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... The Si3050+Si3011 chipset provides two ac termination impedances. The ACIM bit in Register 30 is used to select the ac impedance setting. The two available settings for the Si3050+Si3011 chipset are listed in Table 15. The programmable digital hybrid can be used to further reduce near-end echo for each of the four listed ac termination settings. See " ...
Page 27
... The RNGV bit (Register 24, bit 7) enables or disables the ring validation feature in both normal operating mode and low-power sleep mode. Ring validation affects the behavior of the RDT status bit, the RDTI interrupt, the INT pin, and the RGDT pin. Rev. 1.11 Si3050 + Si3011 27 ...
Page 28
... Ringer Impedance The ring detector in a typical DAA is ac coupled to the line with a large 1 µF, 250 V decoupling capacitor. The ring detector on the Si3011 is resistively coupled to the line. This coupling produces a high ringer impedance to the line of approximately 20 M to meet FCC and TBR21 specifications ...
Page 29
... Set the CALD bit (Register 17, bit 5) to disable the calibration that automatically occurs when going off-hook. b. Set the RCALD bit (Register 25, bit 5) to disable the resistor calibration that automatically occurs when going off-hook c. Set the FOH[1:0] bits (Register 31 bits 6: Rev. 1.11 Si3050 + Si3011 29 ...
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... After allowing the off-hook counter to expire (8 ms), normal transmission and reception can continue. If CID data reception is required, send the appropriate signal to the CO at this time. Figure 24. Implementing Type II Caller ID on the Si3050+Si3011 30 devices on the line are Type II CID compliant, ...
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... The TGA3 and RGA3 bits select either gain or attenuation. The transmit and receive paths can be individually muted with the TXM and RXM bits (Register 15). The signal flow through the Si3050 and the Si3011 is shown in Figures 25–26. DAC ACT Analog Hybrid ...
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... Si3050 + Si3011 5.28. Transhybrid Balance The Si3050 contains an on-chip analog hybrid that performs the 2- to 4-wire conversion and near-end echo cancellation. This hybrid circuit is adjusted for each ac termination setting selected to achieve a minimum transhybrid balance when the line impedance matches the impedance set by ACIM. ...
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... PCLK PFD Figure 27. PLL Clock Synthesizer Table 17. PCM or GCI Highway Mode Selection SCLK Note: Values shown are the states of the pins at the rising edge of RESET. Si3050 + Si3011 VCO DIV M Internal PLL Register SDI Mode Selected X PCM Mode 0 GCI Mode, B2 Channel used ...
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... Si3050 + Si3011 Table 18. Pin Functionality in PCM or GCI Highway Mode Pin Name SDI_THRU SPI Data Throughput pin for Daisy Chaining Operation (Connects to the SDI pin of the subsequent device in the daisy chain) SCLK SDI SDO CS FSYNC PCLK DTX DRX Note: This table denotes pin functionality after the rising edge of RESET and mode selection. ...
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... PCLK FSYNC PCLK_CNT DRX MSB DTX HI-Z MSB Figure 28. PCM Highway Transmission, Short FSYNC, Single Clock Cycle Delayed Transmission I Figure 29. PCM Highway Transmission, Long FSYNC (TXS = RXS = 0, PHCF = 0, TRI = LSB LSB (TXS = RXS = 0, PHCF = 0, TRI = Rev. 1.11 Si3050 + Si3011 HI I-Z 35 ...
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... Si3050 + Si3011 PCLK FSYNC PCLK_CNT DRX DTX HI-Z Figure 30. PCM Highway Transmission, Long FSYNC, Delayed Data Transfer PCLK FSYNC PCLK_CNT DRX M SB DTX HI Figure 31. PCM Highway Double Clocked Transmission, Short FSYNC MSB MSB (TXS = RXS = 10, PHCF = 0, TRI = LSB LSB (TXS = RXS = 0, PHCF = 1, TRI = 1) Rev ...
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... RXS = 0, PHCF = 0, TRI = 1, PCMF = 11) PCLK FSYNC PCLK_CNT DRX MSB DTX HI-Z MSB Sample 1 Figure 33. PCM Highway Transmission, Single Clock Cycle, 16-bit linear mode (TXS = RXS = 0, PHCF = 0, TRI = 1, PCMF = 11, HSSM = Sample 2 Rev. 1.11 Si3050 + Si3011 LSB HI-Z LSB LSB HI-Z LSB 37 ...
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... Si3050 + Si3011 Table 19. µ-Law Encode-Decode Characteristics Segment #Intervals x Interval Size Number 256 128 __________________ Notes: 1. Characteristics are symmetrical about analog 0 with sign bit 2. Digital code includes inversion of both sign and magnitude bits. 38 Value at Segment Endpoints Digital Code 8159 10000000b . . . ...
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... Table 20. A-Law Encode-Decode Characteristics Segment #Intervals x interval size Number 128 Notes: 1. Characteristics are symmetrical about analog 0 with sign bit 2. Digital code includes inversion of all even numbered bits. Si3050 + Si3011 Value at segment endpoints Digital Code 4096 3968 10101010b . . 2143 2015 10100101b . . . 1055 991 10110101b . . . 511 ...
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... Si3050 + Si3011 5.35. SPI Control Interface The control interface to the Si3050 is a 4-wire interface modeled on commonly available micro-controller and serial peripheral devices. The interface consists of four pins: clock (SCLK), chip select (CS), serial data input (SDI), and serial data output (SDO). In addition, the ...
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... Figure 34. SPI Daisy Chain Control Architecture BRCT R SDI0 SDI1 SDI2 SDI3 SDI14 SDI15 Figure 35. Sample SPI Control Byte to Access Channel 0 Si3050 + Si3011 SCLK SDI CS Channel 0 SDO SDITHRU SDI SCLK CS Channel 1 SDO SDITHRU SCLK SDI CS Channel 15 SDO SDITHRU SPI Control Byte 1 0 CID[0] ...
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... Si3050 + Si3011 1 SDI0-15 Figure 36. Sample SPI Control Byte for Broadcast Mode (Write Only) In Figure 35 the CID field this field is decremented in LSB to MSB order, the value decrements for each SDI down the line. The BRCT and R/W bits remain unchanged as the control word passes through the entire chain. A unique CID is presented to each device, and the device receiving a CID value the target of the operation (channel 0 in this case) ...
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... WRITE operation, the last eight bits are ignored read operation, the 8-bit data value is repeated so that the data may be captured during the last half of a data transfer if required by the controller. The Si3050 autodetects the SPI mode (16-bit or 8-bit mode). Si3050 + Si3011 A DDRE Data [7: byte repeated twice ...
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... Si3050 + Si3011 5.36. GCI Highway The Si3050 contains an alternate communication interface to the SPI and PCM highway control and data interface. The general circuit interface (GCI) can be used for the transmission and reception of control and data information onto a GCI highway bus. The PCM and GCI highways are 4-wire interfaces and share the same pins ...
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... Figure 41. Time-Multiplexed GCI Highway Frame Structure 1st Byte MX Transm itter MX MR Receiver MR 1st Byte Figure 42. Monitor Handshake Timing 125 s SF2 SF3 SF4 2nd Byte 3rd Byte ACK ACK 2nd Byte 125 s Rev. 1.11 Si3050 + Si3011 SF5 SF6 SF7 C Channel ACK 3rd Byte 45 ...
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... Si3050 + Si3011 The Idle state is achieved by the MX and MR bits being held inactive (signal is high) for two or more frames. When a transmission is initiated by a host device, an active state (signal is low) is present on the downstream MX bit. This signals to the Si3050 that a transmission has begun on the Monitor channel and the Si3050 should begin accepting data from host device ...
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... New Byte MR: MR bit calculated and transmitted on DTX line. MX: MX bit received data downstream (DRX line). LL: Last look of monitor byte received on DRX line. ABT: Abort indication to internal source. Figure 43. Si3050 Monitor Receiver State Diagram Si3050 + Si3011 Initial State MX Abort ABT MX Any ...
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... Si3050 + Si3011 MR x MXR MR x MXR Idle RQT MR x RQT 1s t Byte RQT nth Byte MR ack RQT Wait for MR x RQT ack MR: MR bit received on DRX line. MX: MX bit calculated and expected on DTX line. MXR: MX bit s am pled on DTX line. CLS: Collis ion within the m onitor data byte on DTX line. ...
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... Si3050 + Si3011 Rev. 1.11 49 ...
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... Si3050 + Si3011 50 Rev. 1.11 ...
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... Monitor Channel section. The definition of the six C/I bits depends on the direction the bits are being sent, either transmitted to the GCI highway bus via the DTX pin or received from the GCI highway bus via the DRX pin. Rev. 1.11 Si3050 + Si3011 byte. The channels whose CMD[6:0] ...
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... Si3050 + Si3011 5.45. Receive SC Channel : MSB 7 6 CIR6 CIR5 CIR4 These bits are defined as follows: CIR6: Reserved CIR5: Reserved CIR4: ONHM CIR3: TGDE CIR2: RG CIR1: OH Data that is received must be consistent and match for at least two consecutive frames to be considered valid. When a new command or status is communicated via the C/I bits, the data must be sent for at least two consecutive frames to be recognized by the Si3050 ...
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... CIT2: Battery Reversal (represents the state of bit 7 of the LVS register) CIT1: TGD Yes P: C/I Primary Register Contents S: C/I Secondary Register Contents Load C/I Register Yes With New C/I Bits Yes 3 4 CIT3 CIT2 C/I Bits Rev. 1.11 Si3050 + Si3011 LSB CIT1 ...
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... Si3050 + Si3011 6. Control Registers Note: Registers not listed here are reserved and must not be written. Register Name 1 Control 1 2 Control 2 3 Interrupt Mask 4 Interrupt Source 5 DAA Control 1 6 DAA Control 2 7 Sample Rate Control 8 Reserved 9 Reserved 10 DAA Control 3 11 System- and Line-Side Device Revision ...
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... Digital loopback across the isolation barrier is disabled Enables digital loopback mode across the isolation barrier. The line-side device must be enabled and off-hook prior to setting this mode. The data path includes the TX and RX filters. 0 Reserved Read returns zero. Si3050 + Si3011 PWMM[1:0] PWME ...
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... Si3050 + Si3011 Register 2. Control 2 Bit D7 D6 Name INTE INTP Type R/W R/W Reset settings = 0000_0011 Bit Name 7 INTE Interrupt Pin Enable The AOUT/INT pin functions as an analog output for call progress monitoring purposes The AOUT/INT pin functions as a hardware interrupt pin. ...
Page 57
... TIP and RING is switched polarity change on TIP and RING does not cause an interrupt on the AOUT/INT pin polarity change on TIP and RING causes an interrupt on the AOUT/INT pin FDTM BTDM DODM R/W R/W R/W Function Rev. 1.11 Si3050 + Si3011 LCSOM TGDM POLM R/W R/W R/W 57 ...
Page 58
... Si3050 + Si3011 Register 4. Interrupt Source Bit D7 D6 Name RDTI ROVI Type R/W R/W Reset settings = 0000_0000 Bit Name 7 RDTI Ring Detect Interrupt ring signal is not occurring ring signal is detected. If the RDTM bit (Register 3) and INTE bit (Register 2) are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be written cleared. ...
Page 59
... Bit 7 of the LVS register has transitioned from from indicating the polarity of TIP and RING is switched. If the POLM bit (Register 3) and INTE bit (Register 2) are set, a hardware interrupt occurs on the AOUT/INT pin. To clear the interrupt, write this bit to 0. Si3050 + Si3011 Function Rev. 1.11 ...
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... Si3050 + Si3011 Register 5. DAA Control 1 Bit D7 D6 Name RDTN Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 RDTN Ring Detect Signal Negative negative ring signal is occurring negative ring signal is occurring. 5 RDTP Ring Detect Signal Positive positive ring signal is occurring. ...
Page 61
... Sample Rate is 8 kHz Sample Rate is 16 kHz. The PCM or the GCI highway continues kHz; thus, twice as many samples are generated per device timeslot. Samples are transmitted in adja- cent timeslots. 2:0 Reserved Read returns zero. Si3050 + Si3011 PDL PDN R/W R/W ...
Page 62
... Si3050 + Si3011 Register 8-9. Reserved Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 Reserved Read returns zero. Register 10. DAA Control 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. Digital Data Loopback. 0 DDL 0 = Normal operation. ...
Page 63
... Name LSID[3:0] Type Reset settings = xxxx_xxxx Bit Name 7:4 LSID[3:0] Line-Side ID Bits. The line-side bits corresponding to the Si3011 are 0100. 3:0 REVA[3:0] System-Side Revision. Four-bit value indicating the revision of the Si3050 (system-side) device. Register 12. Line-Side Device Status Bit D7 D6 Name FDT ...
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... Si3050 + Si3011 Register 13. Line-Side Device Revision Bit D7 D6 Name 1 Type R Reset settings = xxxx_xxxx Bit Name 7 Reserved Read returns zero. 6 Reserved This bit always reads a one. 5:2 REVB[3:0] Line-Side Device Revision. Four-bit value indicating the revision of the line-side device. 1:0 Reserved Read returns zero. ...
Page 65
... IIRE IIR Filter Enable FIR filter enabled for transmit and receive filters. (See Figures 7–10 on page 15 IIR filter enabled for transmit and receive filters. (See Figures 11–16 on page 16.) 3:0 Reserved These bits may be written to a zero or one. Si3050 + Si3011 RXM R/W ...
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... Si3050 + Si3011 Register 17. International Control 2 Bit D7 D6 Name CALZ MCAL Type R/W R/W Reset settings = 0000_0000 Bit Name 7 CALZ Clear ADC Calibration Normal operation Clears the existing ADC calibration data. This bit must be written back to 0 after being set. 6 MCAL Manual ADC Calibration. ...
Page 67
... RNGV RFWE Reserved Read returns zero. Si3050 + Si3011 Function RGDT Half-Wave Full-Wave Validated Ring Envelope Ring Threshold Crossing One-Shot Rev. 1. RFWE ...
Page 68
... Si3050 + Si3011 Register 19. International Control 4 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 OVL Receive Overload Detect. This bit has the same function as ROV (Register 17), but clears itself after the overload is removed. See “5.22.Receive Overload Detection” on page 28. This bit is only masked by the off-hook counter and is not affected by the BTE bit ...
Page 69
... When decremented from the default settings, these bits linearly attenuate the AOUT trans- mit path signal used for call progress monitoring. Setting the bits to all 0s mutes the AOUT transmit path. Attenuation = 20 log(ATM[7:0]/64) 1111_1111 = +12 dB (gain) 0111_1111 = +6 dB (gain) 0100_0000 = 0 dB 0010_0000 = –6 dB (attenuation) 0001_0000 = –12 dB ... 0000_0000 = Mute Si3050 + Si3011 ARM[7:0] R/W Function ATM[7:0] ...
Page 70
... Si3050 + Si3011 Register 22. Ring Validation Control 1 Bit D7 D6 Name RDLY[1:0] Type R/W Reset settings = 1001_0110 Bit Name Ring Delay Bits 1 and 0. 7:6 RDLY[1:0] These bits, in combination with the RDLY[2] bit (Register 23), set the amount of time between when a ring signal is validated and when a valid ring signal is indicated. ...
Page 71
... Ring Timeout DO NOT USE THIS SETTING 128 s m 256 s m 1920 s m Ring Confirmation Count Time 100 s m 150 s m 200 s m 256 s m 384 s m 512 s m 640 s m 1024 s m Rev. 1.11 Si3050 + Si3011 RCC[2:0] R/W 71 ...
Page 72
... Si3050 + Si3011 Register 24. Ring Validation Control 3 Bit D7 D6 Name RNGV Type R/W Reset settings = 0001_1001 Bit Name 7 RNGV Ring Validation Enable Ring validation feature is disabled Ring validation feature is enabled in both normal operating mode and low-power mode. 6 Reserved Always write these bits to zero. ...
Page 73
... Current limiting mode disabled Current limiting mode enabled. This mode limits loop current to a maximum per the TBR21 standard. DC Impedance Selection. 0 DCR dc termination is selected. This mode should be used for all standard applications 800 dc termination is selected. Si3050 + Si3011 Function Rev. 1.11 D2 ...
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... Si3050 + Si3011 Register 27. Reserved Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Do not write to these register bits. Register 28. Loop Current Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 LCS2[7:0] Loop Current Status. Eight-bit value returning the loop current. Each bit represents 1 loop current. ...
Page 75
... Reserved Always write these bits to zero. 1 ACIM AC Impedance Selection. The off-hook ac termination is selected from the following 600 270 + (750 || 150 nF) and 275 + (780 || 150 nF) 0 Reserved Always write this bit to zero. Si3050 + Si3011 FULL2 0 R/W Function Rev. 1.11 ...
Page 76
... Si3050 + Si3011 Register 31. DAA Control 5 Bit D7 D6 Name 0 FOH[1:0] Type Reset settings = 0010_0000 Bit Name 7 Reserved Always write this bit to zero. 6:5 FOH[1:0] Fast Off-Hook Selection. These bits determine the length of the off-hook counter. The default setting is 128 ms 512 128 Reserved Always write this bit to zero. ...
Page 77
... The external relay connecting TIP to an isolated supply is open. In this state, the DAA is unable to determine if the CO has grounded TIP Ring Ground The external relay connecting RING to ground is closed, causing current to flow in RING The external relay connecting RING to ground is open, not allowing current to flow in RING. Si3050 + Si3011 Function Rev. 1. ...
Page 78
... Si3050 + Si3011 Register 33. PCM/SPI Mode Select Bit D7 D6 Name PCML Type R/W R/W Reset settings = 0000_0000 Bit Name PCM Analog Loopback. 7 PCML 0 = Normal operation Enables analog data to be received from the line, converted to digital data and trans- mitted across the ISOcap link. The data passes through the RX filter and is looped back through the TX filter and is transmitted back out to the line ...
Page 79
... Register 36. PCM Receive Start Count—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RXS[7:0] PCM Receive Start Count. PCM Receive Start Count equals the number of PCLKs following FSYNC before data reception begins. Si3050 + Si3011 TXS[7:0] R/W Function Function ...
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... Si3050 + Si3011 Register 37. PCM Receive Start Count—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 RXS[1:0] PCM Receive Start Count. PCM Receive Start Count equals the number of PCLKs following FSYNC before data reception begins ...
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... RGA2 R/W Function Result 0 dB gain or attenuation is applied to the receive path gain is applied to the receive path gain is applied to the receive path attenuation is applied to the receive path attenuation is applied to the receive path. Rev. 1.11 Si3050 + Si3011 RXG2[3:0] R/W 81 ...
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... Si3050 + Si3011 Register 40. TX Gain Control 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 TGA3 Transmit Gain or Attenuation Incrementing the TGA3[3:0] bits results in gaining up the transmit path Incrementing the TGA3[3:0] bits results in attenuating the transmit path. ...
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... Rev. 1.11 Si3050 + Si3011 RXG3[3:0] R/W 83 ...
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... Si3050 + Si3011 Register 42. GCI Control Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3:2 GCIF[1:0] GCI Data Format A-Law µ-Law 8-bit linear. The top 8-bits of the 16-bit linear signal are transferred, and the bottom 8-bits are discarded ...
Page 85
... The current/voltage threshold is triggered by the absolute value of the number in either the LCS2 or LVS register falling below the value in the CVT[7:0] register The current/voltage threshold is triggered by the absolute value of the number in either the LCS2 or LVS register rising above the value in the CVT[7:0] register. Si3050 + Si3011 ...
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... Si3050 + Si3011 Register 45. Programmable Hybrid Register 1 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB1[7:0] Programmable Hybrid Register 1. These bits can be programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the first tap in the eight-tap filter. When this register is set to all 0s, this filter stage does not have an effect on the hybrid response. See the section entitled " ...
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... This register represents the fourth tap in the eight-tap filter. When this register is set to all 0s, this filter stage does not have an effect on the hybrid response. See the section entitled "5.28. Transhybrid Balance" on page 32 for more information on selecting coefficients for the programmable hybrid. Si3050 + Si3011 ...
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... Si3050 + Si3011 Register 49. Programmable Hybrid Register 5 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB5[7:0] Programmable Hybrid Register 5. These bits can be programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the fifth tap in the eight-tap filter. When this register is set to all 0s, this filter stage does not have an effect on the hybrid response. See the section entitled " ...
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... Transhybrid Balance" on page 32 for more information on selecting coefficients for the programmable hybrid. Register 53-58. Reserved Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Do not write to these register bits. Si3050 + Si3011 HYB7[7:0] R/W Function HYB8[7:0] R/W Function ...
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... Si3050 + Si3011 Register 59. RX Gain Control 1 Bit D7 D6 Name 0 0 Type Reset settings = xxxx_xxxx Bit Name 7:3 Reserved Always write these bits to zero. Receive Gain 1. 2 RG1 This bit enables receive path gain adjustment gain applied to hybrid, full scale RX on line = 0 dBm. ...
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... A —IEC/UL60950 3 PPENDIX Introduction Although designs using the Si3011 comply with IEC/ UL60950 3rd Edition and pass all overcurrent and overvoltage tests, there are still several issues to consider. Figure 48 shows two designs that can pass the IEC/ UL60950 overvoltage tests and emissions. The top schematic shows the configuration in which the ferrite beads (FB1, FB2) are on the unprotected side of the sidactor (RV1) ...
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... Si3050 + Si3011 7. Pin Descriptions: Si3050 AOUT/INT Pin # Pin Name 1 SDO Serial Port Data Output. Serial port control data output. 2 SDI Serial Port Data Input. Serial port control data input Chip Select Input. An active low input control signal that enables the SPI Serial port. When inactive, SCLK and SDI are ignored and SDO is high impedance ...
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... Connects to the system digital ground. 19 SCLK Serial Port Bit Clock Input. Controls the serial data on SDO and latches the data on SDI. 20 SDITHRU SDI Passthrough Output. Cascaded SDI output signal to daisy-chain the SPI interface with additional devices. Si3050 + Si3011 Description Rev. 1.11 93 ...
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... Si3050 + Si3011 8. Pin Descriptions: Si3011 Pin # Pin Name 1 QE Transistor Emitter. Connects to the emitter of Q3. 2 DCT DC Termination. Provides dc termination to the telephone network Receive Input. Serves as the receive side input from the telephone network Internal Bias. Provides a bias voltage to the device. 5 C1B Isolation Capacitor 1B ...
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... Pin # Pin Name 14 DCT3 DC Termination 3. Provides dc termination to the telephone network. 15 IGND Isolated Ground. Connects to ground on the line-side interface. 16 DCT2 DC Termination 2. Provides dc termination to the telephone network. Si3050 + Si3011 Description Rev. 1.11 95 ...
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... Region (TSSOP) Si3050+Si3011 FCC/TBR21 Si3050-E-FT Si3011-F-FS Si3050+Si3011 FCC/TBR21 Si3050-E-GT Si3011-F-GS Si3011-F-GT Note: Refer to "10. Product Identification" on page 96 for more information on part naming conventions. 10. Product Identification The product identification number is a finished goods part number or is specified by a finished goods part number, such as a special customer part number ...
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... Package Outline: 20-Pin TSSOP Figure 49 illustrates the package details for the Si3050. Table 24 lists the values for the dimensions shown in the illustration. Figure 49. 20-Pin Thin Shrink Small Outline Package (TSSOP) Si3050 + Si3011 Rev. 1.11 97 ...
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... Si3050 + Si3011 Table 24. 20-Pin TSSOP Package Diagram Dimensions Dimension θ aaa bbb ccc Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components ...
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... Package Outline: 16-Pin SOIC Figure 50 illustrates the package details for the Si3011. Table 25 lists the values for the dimensions shown in the illustration. Figure 50. 16-Pin Small Outline Integrated Circuit (SOIC) Package Si3050 + Si3011 Rev. 1.11 99 ...
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... Si3050 + Si3011 Table 25. 16-Pin SOIC Package Diagram Dimensions Dimension θ aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components ...
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... Package Outline: 16-Pin TSSOP Figure 51 illustrates the package details for the Si3011. Table 26 lists the values for the dimensions shown in the illustration. Figure 51. 16-Pin Thin Shrink Small Outline Package (TSSOP) Si3050 + Si3011 Rev. 1.11 101 ...
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... Si3050 + Si3011 Table 26. 16-Pin TSSOP Package Diagram Dimensions Dimension θ aaa bbb ccc Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AB. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components ...
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... AN72: Ring Detection/Validation with the Si305x DAAs AN77: Silicon DAA Software Guidelines (Si3050) AN81: Emissions Design Considerations AN84: Digital Hybrid with the Si305x DAAs Note: Refer to www.silabs.com for a current list of support documents for this chipset. D UPPORT OCUMENTATION Rev. 1.11 Si3050 + Si3011 103 ...
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... Si3050 + Si3011 N : OTES 104 Rev. 1.11 ...
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... Removed all SPIM references (SPIM bit is never present in any Si3050 device). Removed SnPb package options Minor typo corrections Revision 1.1 to Revision 1.11 The internal System-Side Revision value (REVA[3:0] in Register 11) has been incremented by one for Si3050 revision E. Si3050 + Si3011 Rev. 1.11 105 ...
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... Si3050 + Si3011 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: SiDAAinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...