GD82551ER Intel, GD82551ER Datasheet - Page 50

• Manufacturer Part Number: GD82551ER
• Manufacturer: Intel

Specifications of GD82551ER

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

82551ER — Networking Silicon
7.1.2
42
Figure 14. PCI Command Register
Table 13. PCI Command Register Bits
PCI Command Register
The 82551ER Command register at word address 04h in the PCI configuration space provides
control over the 82551ER’s ability to generate and respond to PCI cycles
register, the 82551ER is logically disconnected from the PCI bus for all accesses except
configuration accesses
Bits three, five, seven, and nine are set to 0b.
register.
15:10
8
6
4
2
1
0
SERR# Enable
Parity Error Response
Memory Write and Invalidate Enable
Bus Master Enable
Memory Space
I/O Space
Bits
Reserved
SERR# Enable
Parity Error Control
Memory Write and
Invalidate Enable
Bus Master
Memory Space
I/O Space
15
Name
Reserved
.
The format of this register is shown in the figure below.
These bits are reserved and should be set to 0b.
This bit controls a device’s ability to enable the SERR# driver. A value of 0b
disables the SERR# driver. A value of 1b enables the SERR# driver. This
bit must be set to report address parity errors. In the 82551ER, this bit is
configurable and has a default value of 0b.
This bit controls a device’s response to parity errors. A value of 0b causes
the device to ignore any parity errors that it detects and continue normal
operation. A value of 1b causes the device to take normal action when a
parity error is detected. This bit must be set to 0b after RST# is asserted. In
the 82551ER, this bit is configurable and has a default value of 0b.
This bit controls a device’s ability to use the Memory Write and Invalidate
command. A value of 0b disables the device from using the Memory Write
and Invalidate Enable command. A value of 1b enables the device to use
the Memory Write and Invalidate command. In the 82551ER, this bit is
configurable and has a default value of 0b.
This bit controls a device’s ability to act as a master on the PCI bus. A
value of 0b disables the device from generating PCI accesses. A value of
1b allows the device to behave as a bus master. In the 82551ER, this bit is
configurable and has a default value of 0b.
This bit controls a device’s response to the memory space accesses. A
value of 0b disables the device response. A value of 1b allows the device
to respond to memory space accesses. In the 82551ER, this bit is
configurable and its default value of 0b.
This bit controls a device’s response to the I/O space accesses
0b disables the device response. A value of 1b allows the device to
respond to I/O space accesses. In the 82551ER, this bit is configurable and
the default value of 0b.
10
0
9
Table 13
8
0
7
describes the bits of the PCI Command
6
Description
0
5
4
0
3
.
2
If a 0 is written to this
1
0
.
Datasheet
A value of