LU82541ER Intel, LU82541ER Datasheet - Page 15

• Manufacturer Part Number: LU82541ER
• Manufacturer: Intel

Specifications of LU82541ER

• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Compliant

3.2.2
3.2.3
3.2.4
Arbitration Signals (2)
Interrupt Signal (1)
System Signals (3)
IDSEL#
DEVSEL#
VIO
REQ#
GNT#
INTA#
CLK
M66EN
RST#
Symbol
Symbol
Symbol
Symbol
I
STS
P
TS
I
TS
I
I
I
Type
Type
Type
Type
Initialization Device Select. The Initialization Device Select signal is used by the
82541ER as a chip select signal during configuration read and write transactions.
Device Select. When the Device Select signal is actively driven by the 82541ER, it
signals notifies the bus master that it has decoded its address as the target of the
current access. As an input, DEVSEL# indicates whether any device on the bus has
been selected.
VIO. The VIO signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI
signaling environment). It is used as the clamping voltage.
Note: VIO should be connected to 3.3V Aux or 5V Aux in order to be compatible with
the pull-up clamps specification.
Request Bus. The Request Bus signal is used to request control of the bus from the
arbiter. This signal is point-to-point.
Grant Bus. The Grant Bus signal notifies the 82541ER that bus access has been
granted. This is a point-to-point signal.
Interrupt A. Interrupt A is used to request an interrupt of the 82541ER. It is an active
low, level-triggered interrupt signal.
PCI Clock. The PCI Clock signal provides timing for all transactions on the PCI bus
and is an input to the 82541ER device. All other PCI signals, except the Interrupt A
(INTA#) and PCI Reset signal (RST#), are sampled on the rising edge of CLK. All other
timing parameters are defined with respect to this edge.
66 MHz Enable. M66EN indicates whether the system bus is enabled for 66MHz
PCI Reset. When the PCI Reset signal is asserted, all PCI output signals are floated
and all input signals are ignored.
Most of the internal state of the 82541ER is reset on the de-assertion (rising edge) of
RST#.
Name and Function
Name and Function
Name and Function
Name and Function
82541ER Gigabit Ethernet Controller
9