DJLXT384LE.B1SE001 Intel, DJLXT384LE.B1SE001 Datasheet - Page 106

• Manufacturer Part Number: DJLXT384LE.B1SE001
• Manufacturer: Intel

Specifications of DJLXT384LE.B1SE001

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Intel
11.1
106
Table 65. Intel
Figure 19. Intel
®
LXT384 Octal T1/E1/J1 S/H PCM Transceiver with JA
Intel
Table 65
Figure 19
Master clock frequency
Master clock tolerance
Master clock duty cycle
Output pulse width
Transmit clock frequency
Transmit clock tolerance
Transmit clock burst rate
Transmit clock duty cycle
E1 TPOS/TNEG pulse width (RZ mode)
TPOS/TNEG to TCLK setup time
TCLK to TPOS/TNEG hold time
Delay time OE Low to driver High Z
Delay time TCLK Low to driver High Z
®
®
®
LXT384 Transceiver Transmit Timing Characteristics
LXT384 Transceiver - Transmit Timing
lists transmit timing characteristics for the LXT384 Transceiver.
TNEG
LXT384 Transceiver Timing
is a transmit timing diagram for the LXT384 Transceiver.
TPOS
TCLK
Parameter
E1
T1
E1
T1
E1
T1
tSUT
Tmpwe1
MCLK
MCLK
Tclke1
Tclkt1
Tclkb
Sym
Toez
Tclkt
Tsut
Tdc
Tht
Tw
Tw
Ttz
–
–
Min.
-100
219
291
236
-50
40
10
20
20
50
–
–
-
-
-
-
2.048
1.544
2.048
1.544
Typ
244
324
60
–
–
–
–
–
–
-
-
-
tHT
Max
+50
100
269
356
252
60
20
90
75
–
–
1
-
-
-
-
MHz
MHz
MHz
MHz
MHz Gapped transmit clock
Unit
ppm
ppm
ns
ns
ns
ns
ns
μs
μs
%
%
Revision Date: November 28, 2005
NRZ mode
RZ mode (TCLK = H for
>16 clock cycles)
Document Number: 248994
Test Condition
Revision Number: 005