SLXT334QE.B3 Intel, SLXT334QE.B3 Datasheet - Page 11

• Manufacturer Part Number: SLXT334QE.B3
• Manufacturer: Intel

Specifications of SLXT334QE.B3

• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

2.0
2.1
2.1.1
2.1.1.1
Datasheet
Functional Description
The LXT334 is a fully integrated, quad line interface unit (QLIU) with four complete, independent
transceivers. It supports G.703 applications at both 2.048 Mbps and 1.544 Mbps. All transceivers
operate at the same frequency, determined by the MCLK input. Refer to the LXT334 block
diagram on page 1.
The front end of each transceiver interfaces with four lines, one pair for transmit, and one pair for
receive. Each transmit/receive line set constitutes a digital data loop for full duplex transmission.
Each transceiver also interfaces with back-end processors through bipolar or unipolar data I/O
channels, and allows control by hardwired pins for stand-alone operation.
Receiver
The four receivers in the LXT334 are identical. The following paragraphs describe the operation of
a single receiver.
The LXT334 receives the input signal at RTIP/RRING via a 1:1 transformer.
Data slicers and a peak detector process the received signal. The peak detector samples the
received signal and determines its maximum value. A data-rate dependent percentage of peak value
goes to the data slicers as a threshold level to ensure an optimum signal-to-noise ratio.
The receiver accurately recovers signals with up to -12 dB of cable loss. The minimum receiver
sensitivity signal level is approximately 500 mV. Regardless of the received signal level, the
LXT334 holds its peak detectors above a minimum level (0.225 V) to provide immunity from
impulse noise.
After the data slicers process the received signal, it is fed to the data and timing recovery section,
and to the receive monitor. The data and timing recovery circuits provide an input jitter tolerance
significantly better than required by G.823 as shown in the Test Specifications section.
The recovered clock is output at RCLK in both bipolar and unipolar modes.
In bipolar mode, recovered data is active High and output at RPOS and RNEG; in unipolar mode
recovered data is active High and output at RDATA.
If CNTL2 is Low, RPOS and RNEG outputs are valid on the falling edge of RCLK. IF CNTL1 is
Low and CNTL2 is High, RPOS and RNEG outputs are valid on the rising edge of RCLK.
Asserting MCLK High disables the clock recovery function and switches all receivers to data
recovery mode. In data recovery mode the RPOS/RNEG outputs are active Low. Asserting MCLK
Low powers all receivers down and holds RPOS/RNEG and RCLK in a high impedance state.
Loss Of Signal Detector
LOS Detection at 2.048 MHz
During 2.048 MHz operation, the Loss of Signal (LOS) detector uses a combination analog and
digital detection scheme and complies with the ITU G.775 recommendation.
Quad Short-Haul Transceiver with Clock Recovery — LXT334
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