MCZ33742EG Freescale, MCZ33742EG Datasheet - Page 30

• Manufacturer Part Number: MCZ33742EG
• Manufacturer: Freescale

Specifications of MCZ33742EG

• Data Rate: 1000Kbps
• Number Of Transceivers: 1
• Standard Supported: CAN 2.0
• Operating Supply Voltage (max): 27V
• Operating Supply Voltage (typ): 5/9/12/15/18/24V
• Operating Supply Voltage (min): 4.5V
• Package Type: SOIC W
• Supply Current: 45mA
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Compliant

mode over-current situation or from forced wake-up, no bits
are set. After the INT pulse, the 33742 accepts SPI command
after a time delay (t
WATCHDOG SOFTWARE IN STOP MODE
provide a “system ok” response before the end of the 33742
watchdog time. Typically an MCU initiates the wake-up of the
33742 through the SPI wake-up (CS activation). The SBC will
awaken and jump into the Normal Request mode. The MCU
has to configure the 33742 to go to either Normal or Standby
mode. The MCU can then decide to return to the Stop mode.
period, the SBC activates the RST pin and jumps into the
Normal Request mode. The MCU can then be re-initialized.
WATCHDOG SOFTWARE (RST AND WDOG)
(SELECTABLE WATCHDOG WINDOW OR
WATCHDOG TIME-OUT)
modes for monitoring the MCU operation. The watchdog
timer may be implemented as either a watchdog window or
watchdog timeout, selectable by SPI (TIM1 sub register, bit
WDW). Default operation is a watchdog window.
(TIM1 sub register, bits WDT0 and WDT1). When a watchdog
window is selected, the closed window is the first part of the
selected period, and the open window is the second part of
the period. (Refer to
page 52.)
time period. Any attempt to clear watchdog in the closed
window will generate a reset. The watchdog is cleared
addressing the TIM1 sub register using the SPI
30
33742
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
If the SBC watchdog is enabled, the application must
If no MCU wake-up occurs within the watchdog time
A watchdog is used in the SBC Normal and Standby
The watchdog period can be set from 10ms to 350ms
The watchdog can only be cleared within the open window
SPI Stop/Sleep
Command
SPI CS
S-1STSPI
Timing Register (TIM1 / 2)
).
33742 in Normal
or Standby mode
Figure 11. Entering the Stop Mode
beginning on
t
CS-STOP
STOP MODE ENTER COMMAND
rising edge of the CS. (Refer to the t
Dynamic Electrical Characteristics
Stop mode is entered, the SBC can wake up from a VDD
regulator over-current detection state. In order to allow time
for the MCU to complete the last CPU instruction and enter
its low power mode, a deglitcher time of 40μs typical is
implemented.
Stop mode.
RST PIN DESCRIPTION
Reset can happen from:
RST AND WDOG OPERATION
operation. RST is activated in the event V
is not triggered. WDOG output is active LOW as soon as RST
goes LOW and stays LOW as long as the watchdog is not
properly reset via SPI. The WDOG output pin is designed as
a push-pull structure that can drive off chip components
signaling, for instance, errant MCU operation.
TIM1 register in not properly accessed. In this case, a
software reset occurs and the WDOG pin is set LOW until the
TIM1 register is properly accessed.
No I
Stop mode is entered at the end of the SPI message at the
Figure
A 33742 output is available to perform a reset of the MCU.
• V
• Power-ON Reset — At 33742 power-on or wake-up from
• Watchdog Timeout — If watchdog is not cleared, the
Table 8
Figure 12
33742 in Stop mode.
threshold (V
V
Sleep mode, the RST pin is maintained LOW until V
is within its operation range.
33742 will pull the RST pin LOW for the duration of the
reset time (t
DD
DD
DD
t
11, page 30, depicts the operation of entering the
over I
Falling Out of Range — If V
IDD-DGLT
returns to the normal voltage.
describes watchdog and reset output modes of
illustrates the device behavior in the event the
DD-DGLT
RSTDUR
RSTTH
Analog Integrated Circuit Device Data
), the RST pin is pulled LOW until
).
33742 in Stop mode.
I
Freescale Semiconductor
table on page 17.) Once
DD
DD
CS-STOP
over I
falls below the reset
DD
DD-DGLT
fall or watchdog
data in the
DD