IDT77V1253L25PGI IDT, Integrated Device Technology Inc, IDT77V1253L25PGI Datasheet - Page 29

• Manufacturer Part Number: IDT77V1253L25PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1253L25PGI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 3
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
2. COUNTERS
software drivers) in evaluating communications conditions. It is anticipated that
these counters will be polled from time to time (user selectable) to evaluate
performance. A separate set of registers exists for each channel of the PHY.
(without roll over) if the counter is read once/second. The Symbol Error counter
and HEC Error counter were given sufficient size to indicate exact counts for
low error-rate conditions. If these counters overflow, a gross condition is
occurring, where additional counter resolution does not provide additional
diagnostic benefit.
Reading Counters
Further reads may be accomplished in the same manner by writing to the
Counter Select Registers.
• Symbol Error Counters
• Transmit Cell Counters
• Receive Cell Counters
• Receive HEC Error Counters
1. Decide which counter value is desired. Write to the Counter Select
Register(s) (0x06, 0x16 and 0x26) to the bit location corresponding to the
desired counter. This loads the High and Low Byte Counter Registers with
the selected counter’s value, and resets this counter to zero.
NOTE: Only one counter may be enabled at any time in each of the Counter Select
Registers.
2. Read the Counter Registers (0x04, 0x14 or 0x24 (low byte)) and (0x05,
0x15 or 0x25 (high byte)) to get the value.
Several condition counters are provided to assist external systems (e.g.
The TxCell and RxCell counters are sized (16 bits) to provide a full cell count
ATM Layer
- 8 bits
- counts all invalid 5-bit symbols received
- 16 bits
- counts all transmitted cells
- 16 bits
- counts all received cells, excluding idle cells and HEC errored
- 5 bits
- counts all HEC errors received
cells
Device
Utopia/DPI
Interface
TC sublayer
Figure 34. Line Loopback
29
VPI/VCI Swapping
77V1253 has the ability to swap parts of the VPI/VCI address space in the header
of receive cells. This function is controlled by the VPI/VCI Swap bits, which are
bit 5 of the Enhanced Control Registers (0x08, 0x18 and 0x28). The portions
of the VPI/VCI that are swapped are shown below. Bits X(7:0) are swapped
with Y(7:0) when the VPI/VCI Swap bit is set and the chip is in DPI mode.
For compatibility with IDT's Switch Star products (77V400 and 77V500), the
X7 X6 X5 X4 X3 X2 X1 X0
Y3 Y2 Y1 Y0
7
7
GFC/VPI
VPI
VCI
sublayer
PMD
HEC
VCI
Y7 Y6 Y5 Y4
PTI
VPI
VCI
CLP
4781 drw 35
0
0
Interface
IDT77V1253
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
4781 drw 51
Line