IDT77V107L25PFI IDT, Integrated Device Technology Inc, IDT77V107L25PFI Datasheet - Page 12

• Manufacturer Part Number: IDT77V107L25PFI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V107L25PFI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Control and Status Interface
Utility Bus
registers within the IDT77V107. These registers are used to select
desired operating characteristics and functions, and to communicate
status to external systems.
bus (AD[7:0]) where the register address is latched via the Address
Latch Enable (ALE) signal.
Read Operation
performed as follows:
Write Operation
Interrupt Operations
provided. They are useful both during ‘normal’ operation, and as diag-
nostic aids. Refer to the Status and Control Register List section.
Register. When this bit is cleared (set to 0), interrupt signalling is
prevented on the respective port. The Interrupt Mask Register allows
individual masking of different interrupt sources. Additional interrupt
IDT77V107
The Utility Bus is a byte-wide interface that provides access to the
The Utility Bus is implemented using a multiplexed address and data
The Utility Bus interface is comprised of the following pins:
AD[7:0], ALE, CS, RD, WR
Refer to the Utility Bus timing waveforms. A register read is
1. Initial condition:
2. Set up register address:
3. Read register data:
A register write is performed as described below:
1. Initial condition:
2. Set up register address:
3. Write data:
A variety of selectable interrupt and signalling conditions are
Overall interrupt control is provided via bit 0 of the Master Control
– RD, WR, CS not asserted (logic 1)
– ALE not asserted (logic 0)
– place desired register address on AD[7:0]
– set ALE to logic 1;
– latch this address by setting ALE to logic 0.
– Remove register address data from AD[7:0]
– assert CS by setting to logic 0;
– assert RD by setting to logic 0
– wait minimum pulse width time (see AC specifications)
– RD, WR, CS not asserted (logic 1)
– ALE not asserted (logic 0)
– place desired register address on AD[7:0]
– set ALE to logic 1;
– latch this address by setting ALE to logic 0.
– place data on AD[7:0]
– assert CS by setting to logic 0;
– assert WR (logic 0) for minimum time (according to timing
specification); reset WR or CS to logic 1 to complete register
write cycle.
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signal control is provided by bit 5 of the Master Control Register. When
this bit is set (=1), receive cell errors will be flagged via interrupt signal-
ling and all other interrupt conditions are masked. These errors include:
clearing bit 5 in the Master Control Register. INT (pin 34) will go to a low
state when an interrupt condition is detected. The external system
should then interrogate the 77V107 to determine which one (or more)
conditions caused this flag, and reset the interrupt for further occur-
rences. This is accomplished by reading the Interrupt Status Register.
Decoding the bits in this byte will tell which error condition caused the
interrupt. Reading these registers also:
problems.
LED Control and Signalling
As an example, the RxLED outputs are described in the truth table:
provide for a two-LED condition indicator. These could also be different
colors to provide simple status indication at a glance. (The minimum
value for R should be 330 ).
TxLED Truth Table
Normal interrupt operations are performed by setting bit 0 and
This leaves the interrupt system ready to signal an alarm for further
The LED outputs provide bi-directional LED drive capability of 8 mA.
As illustrated in the following figure, this could be connected to
– Bad receive HEC
– Short (fewer than 53 bytes) cells
– Received cell symbol error
– clears the (sticky) interrupt status bits in the registers that are
– resets INT
RxLED
TxLED
Cells being transmitted
Cells not being received
Cells being transmitted
Cells not being received
read
State
State
R
R
3.3V
Figure 11
not being received or
(Indicates: Cells are
Low
High
Low
High
being received or
(Indicates: Cells
transmitted)
Pin Voltage
Pin Voltage
transmitted)
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