IDT77105L25TF IDT, Integrated Device Technology Inc, IDT77105L25TF Datasheet - Page 15

• Manufacturer Part Number: IDT77105L25TF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77105L25TF

• Data Rate: 25.6Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

PHY to Magnetics interface
PHY to Magnetics interface
PHY to Magnetics interface
PHY to Magnetics interface
tion is met.
Status and Control Register List
Status and Control Register List
Status and Control Register List
Status and Control Register List
Master Control Register
Master Control Register
Master Control Register
Master Control Register
Address: 0x00
Address: 0x00
Address: 0x00
Address: 0x00
Master Type Initial State
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IDT77105
Figure 21 provides the appropriate connection scheme to the Magnetics Module. The set of values provided will ensure the return Loss specifica-
Nomenclature
R/W = register may be read and written via the utility bus;
R-only or W-only = register may be read-only or write-only via the utility bus;
sticky = register bit is cleared after the register containing it is read.
“0” = ‘cleared’ or ‘not set’
“1” = ‘set’
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RxSOC
RxData
RxClav
RxEnb
RxClk
0
0 = disabled
0 = disabled
0 = disabled
1 = enabled
0 = disabled
0 = cell mode
1 = enabled
Z
UPLO
Controls pin 11, User Programmable Output Latch. Note that the polarity of pin 11 is opposite the polarity of this register bit.
Discard Receive Error Cells
On receipt of any cell with an error (e.g. short cell, invalid symbol or HEC error (if enabled)), the cell will be discarded before
entering the receive FIFO.
Enable Cell Error Interrupts Only
If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only ‘Received Cell Error’ to trigger an interrupt.
Received Cell Errors are: short cell, invalid symbol and HEC error.
Transmit Data Parity Check
Enable checking of TxData[7:0] parity against TxParity.
Discard Received Idle Cells
Enable discarding of received idle (VPI/VCI = 0) cells. There is no indication when such a discard takes place.
Halt Tx
Halts transmission of data and forces both TxD+/- signals to a logic low state.
UTOPIA mode select:
0 = cell mode, 1 = byte mode.
Enable Interrupt Pin (Interrupt Mask Bit)
Enables interrupt output pin. If cleared, INT (pin 53 is always high. If set, INT will drive low when an interrupt occurs.
X
H1
Figure 14 Multi-PHY Receive Waveform
H2
15 of 24
P48
Function
X
Z
X
September 11, 2000
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H1