IDT77V107L25PFI8 IDT, Integrated Device Technology Inc, IDT77V107L25PFI8 Datasheet - Page 15

• Manufacturer Part Number: IDT77V107L25PFI8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V107L25PFI8

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Master Control Register
Address:0x00
IDT77V107
7
6
5
4
3
2
1
0
Bit
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
C1
C2
C3
L1
Component
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
0 = OSC
multiplied by one
1 = discard errored
cells
0 = all interrupts
0 = disabled
1= discard idle cells
0 = not halted
0
1 = enable interrupts
Table 2 Analog Component Values
Initial State
47
47
620
62
62
10k
10k
33
33
82
470pF
470pF
0.1 F
3.3 H
Value
Clock Multiplier Controls whether or not the OSC reference clock input is multiplied by two to generate the line
clock.
Cleared (0) = OSC is multiplied by 1 to generate line clock
Set (1) = OSC is multiplied by 2 to generate line clock
Discard Receive Error Cells On receipt of any cell with an error (e.g. short cell, invalid command mnemonic,
receive HEC error (if enabled)), this cell will be discarded and will not enter the receive FIFO.
Enable Cell Error Interrupts Only If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only
"Received Cell Error" (as defined in bit 6) to trigger interrupt line.
Transmit Data Parity Check Directs TC to check parity of TxDATA against parity bit located in TXPARITY.
Discard Received Idle Cells Directs TC to discard received idle (VPI/VCI = 0 and GFC = 0) cells from PMD without
signalling external systems.
Halt Tx Halts transmission of data from TC to PMD and forces the TxD outputs to the "0" state.
Reserved
Enable Interrupt Pin (Interrupt Mask Bit) Enables the INT output pin. If cleared, pin is always high and interrupt is
masked. If set, an interrupt will be signaled by setting the interrupt pin to "0". It doesn't affect the Interrupt Status Reg-
isters.
±5%
±5%
±5%
±5%
±5%
±5%
±5%
±5%
±5%
±5%
±20%
±20%
±20%
±20%
Tolerance
15 of 24
Magnetics Modules for 25.6 Mbps
Magnetics Modules for 51.2 Mbps
Status and Control Register List
Nomenclature
all sticky bits are read-only
"Reserved" register bits, if written, should always be written "0"
R/W = register may be read and written via the utility bus
R-only or W-only = register is read-only or write-only
sticky = register bit is cleared after the register containing it is read;
“0” = ‘cleared’ or ‘not set’
“1” = ‘set’
Pulse PE-67583 or R4005
TDK TLA-6M103
Pulse R4005
Function
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December 2004