IDT77V106L25TFI8 IDT, Integrated Device Technology Inc, IDT77V106L25TFI8 Datasheet - Page 18

• Manufacturer Part Number: IDT77V106L25TFI8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V106L25TFI8

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Note:
1) The recommended pull up/pull down for R5 and R6 or 10k Ω resistors. This is
not an absolute value and it can be changed if necessary.
STATUS AND CONTROL REGISTER LIST
MASTER CONTROL REGISTER
Address: 0x00
TABLE 3 — ANALOG COMPONENT
VALUES
Nomenclature
"Reserved" register bits, if written, should always be written "0"
R/W = register may be read and written via the utility bus
R-only or W-only = register is read-only or write only
sticky = register bit is cleared after the register containing it is read; all sticky bits are read-only
"0" = "cleared" or "not set"
"1" = "set"
IDT77V106L25
Bit
7
6
5
4
3
2
1
0
Component
Type
R/W
R/W
R/W 0 = all interrupts Enable Cell Error Interrupts Only
R/W
R/W
R/W
R/W
R/W
R5
R6
R1
R2
R3
R4
R7
R8
R9
C1
C2
L1
(1)
(1)
0 = not halted
0 = cell mode
Initial State
Multiplied by
0 = disabled
1 = discard
1 = discard
1 = enable
interrupts
0 = OSC
idle cells
Errored
Cells
one
470pFΩ
470pFΩ
3.3µH
620Ω
110Ω
10kΩ
10kΩ
47Ω
47Ω
82Ω
33Ω
33Ω
Value
Clock Multiplier. Controls whether or not the OSC reference clock inputs is multiplied by two to generate the line
clock.
Cleared (0) = OSC is multiplied by 1 to generate line clock
Set (1) = OSC is multiplied by 2 to generate line clock
Discard Receive Error Cells
On receipt of any cell with an error (e.g. short cell, invalid command mnemonic, receive HEC error (if
enabled), this cell will be discarded and will not enter the receive FIFO.
If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only "Received Cell Error" (as defined in
Transmit Data Parity Cells
Directs TC to check parity of TxDATA against parity bit located in TXPARITY.
Discard Received Idle Cells
Directs TC to discard received idle (VPI/VCI = 0 and GFC = 0) cells from PMD without signaling external systems.
Halt Tx
Halts transmission of data from TC to PMD and forces the TxD output to the "0" state.
UTOPIA Mode Select
0 = cell mode, 1 = byte mode.
Enable Interrupt Pin (Interrupt Mask Bit)
Enables the INT output pin. If cleared, pin is always high and interrupt is masked. If set, an interrupt will be signaled
by setting the interrupt pin to "0". It doesn't affect the Interrupt Status Registers".
bit 6) to trigger interrupt line".
Tolerance
±20%
±20%
±20%
±5%
±5%
±5%
±5%
±5%
±5%
±5%
±5%
±5%
18
Function
TABLE 4 — MAGNETICS MODULES
Pulse PE-67583 or R4005 www.pulseeng.com
TDK TLA-6M103
Pulse R4005
Magnetics Modules for 25.6 Mbps
Magnetics Modules for 51.2 Mbps
www.component.tdk.com
www.pulseeng.com