IDT77V106L25TF IDT, Integrated Device Technology Inc, IDT77V106L25TF Datasheet - Page 2

• Manufacturer Part Number: IDT77V106L25TF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V106L25TF

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

77V106L25 OVERVIEW
network communications as defined by ATM Forum document af-phy-040.000
and ITU-T I.432.5. The physical layer is divided into a Physical Media
Dependent sub layer (PMD) and Transmission Convergence (TC) sub layer.
The PMD sub layer includes the functions for the transmitter, receiver and clock
recovery for operation across 100 meters of category 3 and 5 unshielded
twisted pair (UTP) cable. This is referred to as the Line Side Interface. The TC
sub layer defines the line coding, scrambling, data framing and synchronization.
as a switch core or SAR) through an 8-bit Utopia Level 1 interface.
compatibility with it, but it also has additional register features.
IDT77V106L25
The 77V106L25 is a physical layer interface chip for 25.6Mbps ATM
On the cell side, the 77V106L25 connects to an ATM layer device (such
The 77V106L25 is based on the 77105 and maintains significant register
TXPARITY
TXDATA0
TXDATA1
TXDATA2
TXDATA3
TXDATA4
TXDATA5
TXDATA6
TXDATA7
TXCLAV
TXSOC
RXREF
TXREF
TXLED
TXEN
VDD
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
17 18 19
64
63
62
20
61
Pin 1 Index
Figure 1. Pin Assignments
21 22 23 24 25 26 27 28 29 30
60
IDT77V106
59
58
57
2
56
is an 8-bit muxed address and data bus, controlled by a conventional
asynchronous read/write handshake.
and provide LED indication of receive and transmit status.
OPERATION AT 51.2 Mbps
is also specified to operate at 51.2 Mbps. Except for the doubled bit rate, all other
aspects of operation are identical to the 25.6 Mbps mode.
input pin. OSC is 32 MHz for the 25.6 Mbps line rate, and 64 MHz for the 51.2
Mbps line rate.
operation have a higher bandwidth than magnetics optimized for 25.6 Mbps.
55
Access to these status and control registers is through the utility bus. This
Additional pins permit insertion and extraction of an 8kHz timing marker,
In addition to operation at the standard rate of 25.6 Mbps, the 77V106L25
The rate is determined by the frequency of the clock applied to the OSC
See Figure 16 for recommended line magnetics. Magnetics for 51.2 Mbps
54
53
52
51
31
50
49
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD7
AD6
AD5
AD4
GND
AD3
AD2
AD1
AD0
ALE
CS
RD
WR
RST
INT
RXLED
77v106 drw 02