77V106L25TFG IDT, Integrated Device Technology Inc, 77V106L25TFG Datasheet - Page 3

• Manufacturer Part Number: 77V106L25TFG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 77V106L25TFG

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

TABLE 1 — SIGNAL DESCRIPTION (PART 1 OF 2)
RXDATA[7:0]
Signal Name
Signal Name
Signal Name
TXDATA[7:0]
RXD+, RXD-
TXD+, TXD-
IDT77V106L25
RXPARITY
TXPARITY
RXCLAV
TXCLAV
RXSOC
TXSOC
AD[7:0]
RXCLK
TXCLK
RXEN
TXEN
ALE
WR
CS
RD
Pin Number
Pin Number
Pin Number
11, 10, 9, 8
48, 47, 46,
45, 43, 42,
24, 25, 26,
27, 29, 30
7, 6, 5, 4
31, 32.
58, 57
62, 61
39
38
37
36
20
18
19
23
21
16
17
13
12
14
41, 40.
I/O
I/O
Out
I/O
Out
that
Out
Out
Out
Out
Out
In/
In
In
In
In
In
In
In
In
In
In
In
In
Signal Description
Signal Description
Signal Description
Utility bus address/data bus. The address input is sampled on the falling edge of ALE. Data is output on
this bus when a read is performed. Input data is sampled at the completion of a write operation.
Utility bus address latch enable. Asynchronous input. An address on the AD bus is sampled on the falling
edge of ALE. ALE must be low when the AD bus is being used for data.
Utility bus asynchronous chip select. CS must be asserted to read or write an internal register. It may remain
asserted at all times if desired.
Utility bus read enable. Active low asynchronous input. After latching an address, a read is performed by
deasserting WR and asserting RD and CS.
Utility bus write enable. Active low asynchronous input. After latching an address, a write is performed by
deasserting RD, placing data on the AD bus, and asserting WR and CS. Data is sampled when WR or
CS is deasserted.
Utopia Receive Cell Available. "1" indicates that the receive FIFO contains a complete cell. "0" indicates
Utopia Receive Clock. This is a free running clock input.
Utopia Receive Data. When one of the four ports is selected, the 77V106L25 transfers received cells to
an ATM device across the bus. Also see RXPARITY.
Utopia Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA
bus.
Utopia Receive Data Parity. Odd parity over RXDATA[7:0].
Utopia Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA.
Utopia Transmit Cell Available. "1" indicates that the transmit FIFO has room available for at least one complete
cell. "0" indicates that it does not.
Utopia Transmit Clock. This is a free running clock input.
Utopia Transmit Data. An ATM device transfer cell across this bus to the 77V106L25 for transmission. Also
see TXPARITY.
Utopia Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA
bus.
Utopia Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is checked and errors are indicated
in the Interrupt Status Registers, as enabled in the Master Control Register. No other action is taken in the
even of an error. Tie high or low if unused.
Utopia Transmit Start of Cell. Asserted coincident with the first word the first word of data for each cell on
TXDATA.
Positive and negative receive differential input pair.
Positive and negative transmit differential output pair.
it does not.
Utopia Bus Signals
Utility Bus Signals
Line Side Signals
3