AD8019ARU-REEL Analog Devices Inc, AD8019ARU-REEL Datasheet - Page 11

• Manufacturer Part Number: AD8019ARU-REEL
• Manufacturer: Analog Devices Inc

Specifications of AD8019ARU-REEL

• Power Supply Requirement: Single/Dual
• Package Type: TSSOP
• Slew Rate: 450V/us
• Pin Count: 14
• Lead Free Status / RoHS Status: Not Compliant

GENERAL INFORMATION
The AD8019 is a voltage feedback amplifier with high output
current capability. As a voltage feedback amplifier, the AD8019
features lower current noise and more applications flexibility than
current feedback designs. It is fabricated on Analog Devices’
proprietary High Voltage eXtra Fast Complementary Bipolar
Process (XFCB-HV), which enables the construction of PNP
and NPN transistors with similar f
process is dielectrically isolated to eliminate the parasitic and
latch-up problems caused by junction isolation. These features
enable the construction of high-frequency, low-distortion amplifiers.
POWER-DOWN FEATURE
A digitally programmable logic pin (PWDN) is available on the
TSSOP-14 package. It allows the user to select between two
operating conditions, full on and shutdown. The DGND pin is
the logic reference. The threshold for the PWDN pin is typically
1.8 V above DGND. If the power-down feature is not being
used, it is better to tie the DGND pin to the lowest potential
that the AD8019 is tied to and place the PWDN pin at a poten-
tial at least 3 V higher than that of the DGND pin, but lower
than the positive supply voltage.
POWER SUPPLY AND DECOUPLING
The AD8019 can be powered with a good quality (i.e., low-noise)
supply anywhere in the range from +12 V to 12 V. In order to
optimize the ADSL upstream drive capability of 13 dBm and
maintain the best Spurious Free Dynamic Range (SFDR), the
AD8019 circuit should be powered with a well-regulated supply.
Careful attention must be paid to decoupling the power supply.
High quality capacitors with low equivalent series resistance
(ESR) such as multilayer ceramic capacitors (MLCCs) should
be used to minimize supply voltage ripple and power dissipa-
tion. In addition, 0.1 F MLCC decoupling capacitors should
be located no more than 1/8 inch away from each of the power
supply pins. A large, usually tantalum, 10 F to 47 F capacitor
is required to provide good decoupling for lower frequency
signals and to supply current for fast, large signal changes at
the AD8019 outputs.
POWER DISSIPATION
It is important to consider the total power dissipation of the
AD8019 in order to properly size the heat sink area of an appli-
cation. Figure 3 is a simple representation of a differential driver.
With some simplifying assumptions we can estimate the total
power dissipated in this circuit. If the output current is large
compared to the quiescent current, computing the dissipation
in the output devices and adding it to the quiescent power dissipa-
tion will give a close approximation of the total power dissipation in
the package. A factor
due to the Class A/B operation of the output stage. It can be
estimated by subtracting the quiescent current in the output
stage from the total quiescent current and ratioing that to the
total quiescent current. For the AD8019,
(~0.6-1) corrects for the slight error
T
s in the 4 GHz region. The
= 0.833.
Remembering that each output device only dissipates for half
the time gives a simple integral that computes the power for
each device:
The total supply power can then be computed as:
In this differential driver, V
amplifier, so 2 V
impedance seen by the differential driver, including back
termination. Now, with two observations the integrals are easily
evaluated. First, the integral of V
rms value of V
average rectified value of V
deviation, or MAD. It can be shown that for a DMT signal, the
MAD value is equal to 0.8 times the rms value.
For the AD8019 operating on a single 12 V supply and delivering a
total of 16 dBm (13 dBm to the line and 3 dBm to the matching
network) into 17.3
transformer plus back termination), the dissipated power is:
Using these calculations and a
package and 100 C/W for the SOIC, Tables I–IV show junc-
tion temperature versus power delivered to the line for several
supply voltages while operating with an ambient temperature
of 85 C. The shaded areas indicate operation at a junction
temperature over the absolute maximum rating of 150 C, and
should be avoided.
Table I. Junction Temperature vs. Line Power and Operating
Voltage for TSSOP
P
13
14
15
16
17
18
LINE
P
TOT
, dBm
P
TOT
4 0 8
( .
4
O
. Second, the integral of | V
V rms V
(
+V
–V
V
O
O
132
134
136
139
141
143
S
S
S
is the voltage across R
12
2
1
|
V
= 332 mW + 40 mW
(100
+V
O
(
O
S
V
|
O
–
S
, sometimes called the mean average
O
= 372 mW
V rms
–
V
is the voltage at the output of one
O
V
reflected back through a 1:1.7
O
R
O
2
O
JA
L
)
)
2
V
of 90 C/W for the TSSOP
is simply the square of the
2
SUPPLY
(
)
1
2
2
R
–V
134
137
139
141
144
147
V
R
L
O
O
2
1
12.5
L
)
L
. R
O
I V
2
| is equal to the
+V
–V
Q
L
AD8019
S
S
is the total
S
I V
Q
P
S
OUT
137
139
141
144
147
150
13
P
OUT