HS1-82C54RH-8 Intersil, HS1-82C54RH-8 Datasheet - Page 7

• Manufacturer Part Number: HS1-82C54RH-8
• Manufacturer: Intersil

Specifications of HS1-82C54RH-8

• Lead Free Status / RoHS Status: Supplier Unconfirmed

The Status Register, shown in the figure, when latched,
contains the current contents of the Control Word Register
and status of the output and null count flag. (See detailed
explanation of the Read-Back Command.)
The actual counter is labeled CE for “Counting Element”. It is
a 16-bit presettable synchronous down counter.
OLM and OLL are two 8-bit latches. OL stands for “Output
Latch”, subscripts M and L for “Most significant byte” and
“Least significant byte”, respectively. Both are normally
referred to as one unit and called just OL. These latches
normally “follow” the CE, but if a suitable Counter Latch
Command is sent to the HS-82C54RH, the OL latches the
present count until read by the CPU and then returns to
“following” the CE. One latch at a time is enabled by the
counter’s Control Logic to drive the internal bus. This is how
the 16-bit Counter communicates over the 8-bit internal bus.
Note that the CE itself cannot be read; whenever you read
the count, it is the OL that is being read.
Similarly, there are two 8-bit registers called CRM and CRL
(for “Count Register”). Both are normally referred to as one
unit and called just CR. When a new count is written to the
Counter, the count is stored in the CR and later transferred
to the CE. The Control Logic allows one register at a time to
be loaded from the internal bus. Both bytes are transferred to
the CE simultaneously. CRM and CRL are cleared when the
Counter is programmed for one byte counts (either most
significant byte only or least significant byte only) the other
byte will be zero. Note that the CE cannot be written into;
whenever a count is written, it is written into the CR.
The Control Logic is also shown in the diagram. CLKn,
GATEn, and OUTn are all connected to the outside world
through the Control Logic.
CLK N
REGISTER
CONTROL
CONTROL
GATE N
WORD
LOGIC
FIGURE 7. COUNTER INTERNAL BLOCK DIAGRAM
OUT N
REGISTER
STATUS
STATUS
LATCH
INTERNAL BUS
7
CRM
OLM
CE
CRL
OLL
HS-82C54RH
HS-82C54RH System Interface
The HS-82C54RH is treated by the system software as an
array of peripheral I/O ports; three are Counters and the
fourth is a Control Word Register for MODE programming.
Basically, the select inputs A0, A1 connect to the A0, A1
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method or
it can be connected to the output of a decoder, such as a
Intersil HD-6440 for larger systems.
Operational Description
General
After power-up, the state of the HS-82C54RH is undefined. The
Mode, count value, and output of all Counters are undefined.
How each Counter operates is determined when it is
programmed. Each Counter must be programmed before it
can be used. Unused Counters need not be programmed.
Programming The HS-82C54RH
Counters are programmed by writing a Control Word and
then an initial count.
All Control Words are written into the Control Word Register,
which is selected when A1, A0 = 11. The Control Word
specifies which Counter is being programmed.
By contrast, initial counts are written into the Counters, not
the Control Word Register. The A1, A0 inputs are used to
select the Counter to be written into. The format of the initial
count is determined by the Control Word used.
Write Operations
The programming procedure for the HS-82C54RH is very
flexible. Only two conventions need to be remembered:
1. For each Counter, the Control Word must be written
2. The initial count must follow the count format specified in
before the initial count is written.
the Control Word (least significant byte only, most
OUT GATE CLK
A1
COUNTER
FIGURE 8. HS-82C54RH SYSTEM INTERFACE
A1
A0
0
A0
CS
ADDRESS BUS (16)
OUT GATE CLK
CONTROL BUS
HS-82C54RH
DATA BUS (8)
COUNTER
D0-D7
1
8
OUT GATE CLK
COUNTER
RD
2
I/OR I/OW
WR