PCF8573TD NXP Semiconductors, PCF8573TD Datasheet - Page 7

PCF8573TD

Manufacturer Part Number
PCF8573TD
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCF8573TD

Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Pin Count
16
Mounting
Surface Mount
Time Format
HH:MM:SS
Lead Free Status / RoHS Status
Not Compliant
Philips Semiconductors
8
The I
(SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1
See Fig.4. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals.
8.2
Refer to Fig.5. Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data
line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the
clock is HIGH is defined as the stop condition (P).
2003 Jan 27
handbook, full pagewidth
handbook, full pagewidth
Clock/calendar with serial I/O
CHARACTERISTICS OF THE I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line
Bit transfer
Start and stop conditions
SDA
SCL
START condition
SDA
SCL
S
2
C-BUS
Fig.5 Definition of start and stop conditions.
data valid
data line
stable;
Fig.4 Bit transfer.
7
allowed
change
of data
STOP condition
MBC621
P
MBC622
SDA
SCL
Product specification
PCF8573

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