UPD4990AG Renesas Electronics America, UPD4990AG Datasheet - Page 15

• Manufacturer Part Number: UPD4990AG
• Manufacturer: Renesas Electronics America

Specifications of UPD4990AG

• Lead Free Status / RoHS Status: Supplier Unconfirmed

DATA INPUT/OUTPUT TIMING DIAGRAM
TIMING DIAGRAM OF DATA INPUT AND OUTPUT
CLK
DATA
IN
OUT
ENBL
DATA
OUT
Note: Reading-in timing of CPU (Trailing edge of CLK).
CLK
DATA OUT
DATA IN
"1" s.
"1" s.
0 1 2 3 4 5 6 7 8 9 1011
"10" s.
"10" s.
t
t
t
dC-O
DSU
DHLD
"1" min.
"1" min.
V
V
:
:
:
IH
IL
1 s MAX. (R
1 s MIN.
1 s MIN.
t
DSU
Command (C
Command (C
CS = "H"
Figure 4.
Figure 5.
4041424344454647
V
V
"1" year "10" year
"1" year "10" year
IH
IL
L
= 33 k , C
2
3
, C
', C
1
2
, C
', C
0
) is set to (1, 1, 1).
0
L
') is set to [0001] (Register Shift Mode).
= 25 pF)
Written-in data LSB ("H")
appears at output.
t
dC-O
t
V
DHLD
V
OH
OL
'70
July 16 (Sun.)
2 hours 24 minutes
35 seconds.
'86
November 25 (Sat.)
2 hours 23 minutes
49 seconds.
PD4990A
INPUT
TIMING
OUTPUT
TIMING
13