MC100ES6130DTR2 IDT, Integrated Device Technology Inc, MC100ES6130DTR2 Datasheet - Page 2

• Manufacturer Part Number: MC100ES6130DTR2
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of MC100ES6130DTR2

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 2000MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.8/3.8V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: HSTL/LVPECL
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Not Compliant

IDT™ / ICS™ PECL CLOCK DRIVER
Table 1. Pin Description
Table 2. Truth Table
Table 3. General Specifications
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
θ
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. Z = HIGH to LOW Transition
1, 2, 3, 4, 5, 6,
JA
11, 12, 13, 14
MC100ES6130
2.5/3.3V, 1:4 PECL CLOCK DRIVER WITH 2:1 INPUT MUX
X = Don’t Care
Thermal Resistance (Junction-to-Ambient)
Number
IN0
7, 8
10
15
16
H
X
X
Z
X
L
9
Q0 to Q3
Q0 to Q3
IN0, IN0
IN1, IN1
IN_SEL
Name
IN1
(1)
H
V
V
X
X
X
Z
L
EN
CC
EE
LVPECL differential outputs: Terminate with 50Ω to V
the unused output with 50Ω to V
Negative power supply: For LVPECL applications, connect to GND.
LVPECL compatible 2:1 mux input signal select: When IN_SEL is LOW, the IN0 input pair is selected.
When IN_SEL is HIGH, the IN1 input pair is selected. Includes a 75 kΩ pulldown. Default state is LOW and
IN0 is selected.
LVPECL, HSTL clock or data inputs. Internal 75 kΩ pulldown resistors on IN0 and IN1. Internal 75 kΩ
pullup and 75 kΩ pulldown resistors on IN0, IN1. IN0, IN1 default condition is V
IN1 default condition is LOW when left floating.
LVPECL compatible synchronous enable: When EN goes HIGH, Q
on the next LOW input clock transition. Includes a 75 kΩ pulldown. Default state is LOW when left floating.
The internal latch is clocked on the falling edge of the input (IN0, IN1).
Positive power supply: Bypass with 0.1 µF//0.01 µF low ESR capacitors.
IN_SEL
Characteristics
H
H
H
L
L
L
Human Body Model
Machine Model
Charged Device Model
0 LFPM, 16 TSSOP
500 LFPM, 16 TSSOP
EN
H
H
L
L
L
L
CC
– 2 V.
Q
2
H
H
L
L
L
L
Description
CC
– 2 V. For single-ended applications, terminate
OUT
will go LOW and Q
MC100ES6130 REV. 4 MARCH 3, 2009
CC
> 2000 V
> 1500 V
138°C/W
108°C/W
> 200 V
Value
75 kΩ
75 kΩ
/2 when left floating. IN0,
OUT
will go HIGH