CY29949AC Cypress Semiconductor Corp, CY29949AC Datasheet - Page 3

• Manufacturer Part Number: CY29949AC
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Dividerr

Specifications of CY29949AC

• Number Of Clock Inputs: 3
• Output Frequency: 200MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.63V
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Signal Type: LVCMOS/LVPECL/LVTTL
• Mounting: Surface Mount
• Pin Count: 52
• Quiescent Current: 7mA
• Lead Free Status / RoHS Status: Not Compliant

Maximum Ratings
Maximum Input Voltage Relative to V
Maximum Input Voltage Relative to V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature:................................ –40°C to +85°C
Maximum ESD Protection .............................................. 2 kV
Maximum Power Supply:................................................ 5.5V
Maximum Input Current: ............................................ ±20 mA
DC Parameters
Document #: 38-07289 Rev. *E
V
V
I
I
V
V
V
V
I
I
Zout
C
Notes
IL
IH
DDQ
DD
Parameter
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The V
5. Driving series or parallel terminated 50Ω (or 50Ω to V
IL
IH
PP
CMR
OL
OH
in
range and the input lies within the V
CMR
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the V
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range
PECL_CLK
Output Low Voltage
Output High Voltage
Quiescent Supply Current
Dynamic Supply Current
Output Impedance
Input Capacitance
(V
Description
DD
[2]
= V
DDC
PP
[3]
[3]
[5]
specification.
[5]
= 3.3V ±10% or 2.5V ±5%, over the specified temperature range)
SS
DD
[4]
:............. V
:............. V
V
V
All other inputs
V
V
All other inputs
V
V
I
I
I
V
CL = 30 pF
V
CL = 30 pF
V
CL = 30 pF
V
CL = 30 pF
V
V
OL
OH
OH
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
/2) transmission lines.
= 20 mA
= –20 mA, V
= –20 mA, V
= 3.3V, PECL_CLK single ended
= 2.5V, PECL_CLK single ended
= 3.3V, PECL_CLK single ended
= 2.5V, PECL_CLK single ended
= 3.3V
= 2.5V
= 3.3V, Outputs at 100 MHz,
= 3.3V, Outputs at 160 MHz,
= 2.5V, Outputs at 100 MHz,
= 2.5V, Outputs at 160 MHz,
= 3.3V
= 2.5V
DD
SS
– 0.3V
+ 0.3V
Conditions
DD
DD
= 3.3V
= 2.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions must be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, V
V
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
< (V
in
or V
in
and V
out
) < V
V
V
DD
DD
out
2.135
1.49
1.10
1.75
Min
V
300
2.0
2.5
1.8
SS
12
14
DD
–
–
–
–
–
–
–
–
–
SS
– 2.0
– 1.2
should be constrained to the range:
or V
DD
).
Typ
200
330
140
235
15
18
5
–
–
–
–
–
–
–
–
–
–
–
–
–
4
V
V
DD
DD
1.825
–100
1000
Max
1.45
2.42
V
100
0.8
2.0
0.4
18
22
–
–
7
–
–
–
–
–
DD
– 0.6
– 0.6
CY29949
Page 3 of 7
Unit
mV
mA
mA
CMR
µA
pF
Ω
V
V
V
V
V
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