92HD81B1C5NLGXUAX Integrated Device Technology (Idt), 92HD81B1C5NLGXUAX Datasheet - Page 39

• Manufacturer Part Number: 92HD81B1C5NLGXUAX
• Description: Audio Codec 2ADC / 2DAC 24-Bit 48-Pin VFQFPN EP Tray
• Manufacturer: Integrated Device Technology (Idt)
• Type: General Purposer

Specifications of 92HD81B1C5NLGXUAX

• Package: 48VFQFPN EP
• Adc/dac Resolution: 24 Bit
• Number Of Channels: 2ADC /2 DAC
• Sampling Rate: 192 KSPS
• Number Of Dac Outputs: 8
• Number Of Dacs: 2
• Operating Supply Voltage: 1.5|1.8|3.3|4|4.75|5 V

92HD81
SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
IDT™ CONFIDENTIAL
2.22.4. EAPD
2.22.5. Analog PC_Beep
2.22.6. Firmware/Software Requirements:
DAC 0
EAPD
(pin)
Since the Aux Audio mode overrides the default behavior but not the actual port settings when in
reset, the logical state of the EAPD pin must be overridden as well. When Aux Audio mode is
enabled and the part is in reset as described above, the logical state of EAPD will be 1 (External
Amplifier Powered Up) unless held low by an external circuit. This ensures that audio pass-thru and
analog PC_Beep will be supported.
Analog PC_Beep may be supported in Aux Audio mode. By default, analog PC_Beep is disabled. If
the CODEC is programmed to enable analog PC_Beep and Aux Audio mode is enabled, the next
time reset is asserted, the analog PC_Beep pin will be mixed at each of the active outputs.
If it is desirable to stop the HD Audio bus while the CODEC is in D3 under OS control per ECR-15b,
Firmware must disable the AUX Audio Mode support in the CODEC prior to loading the OS. If Aux
Audio Mode is not disabled in the CODEC, the CODEC will report to the OS driver that stopping the
bus clock while the CODEC is in D3 is not supported or not available.
1.default value for Aux Audio Enable is determined by bond option.
0
1
1
1
Support
Enable
Aux
X
0
1
1
1
MixerOutVol
detect
D MIc
X
X
1
1
DAC0
DAC1
DAC2
Digital PC Beep
detect
Port F
X
X
0
1
Analog Beep
Ports A, B, C,
D, E detect
39
Σ
DMIC_0
NA
NA
NA
NA
+0/+10/+20/+30 dB
+0/+10/+20/+30 dB
LO
LO
Boost
Boost
Boost
DMIC routed through CODEC DAC to port E. DMIC
Clock provided from external source through DCLK
DMIC
CODEC DAC and Port E disabled
PORT E
Pin Complex
Pins 15/16
PORT C
Pin Complex
Pins 19/20
Mic Bias
pin. 3.072MHz typ.
Widget controlled
Port E behavior
DMIC_0
DMIC_CLK
Pin 4
Pin 2
disabled
Aux Audio Out
(Disabled if Port
F in use)
MIC Jack
(Disabled)
V 0.987 11/09
92HD81