71M6543F-DB-CT Maxim Integrated Products, 71M6543F-DB-CT Datasheet - Page 113
71M6543F-DB-CT
Manufacturer Part Number
71M6543F-DB-CT
Description
Power Management Modules & Development Tools 71M6543 Eval Kit
Manufacturer
Maxim Integrated Products
Datasheet
1.71M6543F-DB.pdf
(157 pages)
Specifications of 71M6543F-DB-CT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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v1.2
Name
PLL_OK
PLL_FAST
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
PLS_INV
PORT_E
PRE_E
PREBOOT
RCMD[4:0]
RESET
RFLY_DIS
SFR FC[4:0] 0
SFR F9[4]
SFRB2[7]
Location Rst Wk Dir
210A[7:0] FF FF R/W
210B[7:0]
210C[0]
270C[5]
210C[3]
2200[4]
2704[5]
2200[3]
0
0
0
0
0
0
–
0
0
0
0
0
0
0
0
–
0
0
0
© 2008–2011 Teridian Semiconductor Corporation
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
Description
Indicates that the clock generation PLL is settled.
Controls the speed of the PLL and MCK.
1 = 19.66 MHz (XTAL * 600)
0 = 6.29 MHz (XTAL * 192)
PLS_MAXWIDTH[7:0] determines the maximum width of the pulse (low-going pulse if
PLS_INV=0 or high-going pulse if PLS_INV=1). The maximum pulse width is
(2*PLS_MAXWIDTH[7:0] + 1)*T
clock cycles. If PLS_INTERVAL[7:0] = 0 or PLS_MAXWIDTH[7:0] = 255, no pulse
width checking is performed and the output pulses have 50% duty cycle. See
VPULSE and
PLS_INTERVAL[7:0] determines the interval time between pulses. The time between
output pulses is PLS_INTERVAL[7:0]*4 in units of CK_FIR clock cycles. If
PLS_INTERVAL[7:0] = 0, the FIFO is not used and pulses are output as soon as the CE
issues them. PLS_INTERVAL[7:0] is calculated as follows:
PLS_INTERVAL[7:0]
frame / 4 )
For example, since the 71M6543 CE code is written to generate 6 pulses in one integration
interval, when the FIFO is enabled (i.e., PLS_INTERVAL[7:0] ≠ 0) and that the frame
duration is 1950 CK_FIR clock cycles, PLS_INTERVAL[7:0] should be written with
Floor(1950 / 6 / 4) = 81 so that the five pulses are evenly spaced in time over the
integration interval and the last pulse is issued just prior to the end of the interval. See
2.3.6.2 VPULSE and
Inverts the polarity of WPULSE and VARPULSE. Normally, these pulses are active low.
When inverted, they become active high. PLS_INV has no effect on XPULSE or
YPULSE.
Enables outputs from the SEGDIO0-SEGDIO15 pins. PORT_E = 0 blocks the momentary
output pulse that occurs when SEGDIO0-SEGDIO15 are reset on power-up.
Enables the 8x pre-amplifier.
Indicates that pre-boot sequence is active.
When the MPU writes a non-zero value to RCMD, the 71M6543 issues a command to
the appropriate remote sensor. When the command is complete, the 71M6543 clears
RCMD.
When set, writes a one to WF_RSTBIT and then causes a reset.
Controls how the 71M6543 drives the power pulse for the 71M6xxx. When set, the
power pulse is driven high and low. When cleared, it is driven high followed by an open
circuit fly-back interval.
WPULSE.
= Floor ( Mux frame duration in CK_FIR cycles / CE pulse updates per Mux
WPULSE.
I
. Where T
I
is PLS_INTERVAL[7:0] in units of CK_FIR
71M6543F/H and 71M6543G/GH Data Sheet
2.3.6.2
113
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