AX5051-QFN28-TU AXSEM, AX5051-QFN28-TU Datasheet
AX5051-QFN28-TU
Specifications of AX5051-QFN28-TU
Related parts for AX5051-QFN28-TU
AX5051-QFN28-TU Summary of contents
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... DATASHEET AX5051 Version 1.9 ...
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... Document Type Datasheet Document Status Document Version Version 1.9 Product AX5051 Version 1.9 Datasheet AX5051 ...
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... RF Frequency Generation Subsystem (Synthesizer) ................................................................ 14 Transmitter...................................................................................................................................... 15 Receiver ......................................................................................................................................... 16 SPI Timing........................................................................................................................................ 18 5. Circuit Description ................................................................................................................... 19 5.1. Voltage Regulator ....................................................................................................................... 20 5.2. Crystal Oscillator........................................................................................................................... 20 5.3. SYSCLK Output.............................................................................................................................. 21 5.4. Power-on-reset (POR) and RESET_N Input ................................................................................ 21 5.5. RF Frequency Generation Subsystem....................................................................................... 21 VCO ................................................................................................................................................ 22 VCO Auto-Ranging ...................................................................................................................... 22 Loop Filter and Charge Pump .................................................................................................... 22 Version 1.9 3 Table of Contents Datasheet AX5051 ...
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... PWRMODE Register ................................................................................................................ 29 5.15. Serial Peripheral Interface (SPI) ............................................................................................ 31 SPI Timing........................................................................................................................................ 31 6. Register Bank Description ....................................................................................................... 32 6.1. Control Register Map................................................................................................................... 33 7. Application Information.......................................................................................................... 37 7.1. Typical Application Diagram ..................................................................................................... 37 7.2. Antenna Interface Circuitry........................................................................................................ 38 Single-Ended Antenna Interface ............................................................................................... 38 Dipole Antenna Interface ........................................................................................................... 39 7.3. Voltage Regulator ....................................................................................................................... 39 Version 1.9 Datasheet AX5051 ...
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... QFN28 Package Information .................................................................................................. 40 8.1. Package Outline QFN28 5x5 mm 8.2. QFN28 Soldering Profile ............................................................................................................... 41 8.3. QFN28 Recommended Pad Layout ......................................................................................... 42 8.4. Assembly Process ......................................................................................................................... 42 Stencil Design & Solder Paste Application ............................................................................... 42 9. Life Support Applications ........................................................................................................ 44 10. Contact Information ................................................................................................................ 45 Version 1.9 ............................................................................................. Table of Contents Datasheet AX5051 ...
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... Toys • Wireless audio • Wireless networks • Wireless USB • Access control • Remote keyless entry • ARIB compatible • Pointing devices and keyboards • Active RFID • RFID base station transmitter • 433/868/915 MHz SRD band systems Datasheet AX5051 ...
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... AGC PGAs ANTP 4 5 ANTN PA F OUT Crystal Oscillator RF Frequency F XTAL typ. Generation 16 MHz Subsystem Divider Figure 1 Functional block diagram of the AX5051 Version 1.9 AX5051 Digital IF De- ADC channel modulator filter RSSI AGC Modulator Communication Controller & Chip configuration Voltage POR Regulator ...
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... Regulated output voltage P VDD pins must be connected to this supply voltage A 1µF low ESR capacitor to GND must be connected to this pin N Not to be connected N Not to be connected A Crystal oscillator input/output A Crystal oscillator input/output I/O = digital input/output signal N = not to be connected P = power or ground Datasheet AX5051 ...
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... Pinout Drawing NC 1 VDD 2 GND 3 4 ANTP ANTN 5 GND 6 VDD 7 Version 1 VDD_IO 20 IRQ 19 AX5051 TST3 18 MOSI 17 MISO 16 CLK Figure 2: Pinout drawing (Top view) 9 Pin Function Descriptions Datasheet AX5051 ...
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... Electrostatic handling es T Operating temperature amb T Storage temperature stg T Junction Temperature j Version 1.9 CONDITION MIN -0.5 -10 -100 -0.5 -0.5 HBM -2000 -40 -65 MAX UNIT 5.5 V 100 mA 800 mW 15 dBm 10 mA 100 5.5 V 5.5 V 2000 V 85 °C 150 °C 150 °C Datasheet AX5051 ...
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... MHz, 0 dBm 868 MHz, max power 868 MHz, min power 433 MHz, 10 dBm 433 MHz, 0 dBm 433 MHz, max power 433 MHz, min power 11 Specifications TYP. MAX. UNIT 27 85 °C 3.0 3.6 V 3.0 3.6 V 1.7 V 2.5 2 300 mV 0.5 µ Datasheet AX5051 ...
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... Input voltage, low IL V Input voltage, high IH I Input leakage current L DIGITAL OUTPUTS I Output Current, high OH I Output Current, low OL I Tri-state output leakage current OZ Version 1.9 CONDITION MIN. TYP. 1.9 1.2 2 -10 MAX. UNIT µ µA Datasheet AX5051 ...
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... XTALOSCGM =0101 6 XTALOSCGM =0110 6.5 XTALOSCGM =0111 7 XTALOSCGM =1000 7.5 XTALOSCGM =1001 8 XTALOSCGM =1010 8.5 XTALOSCGM =1011 9 XTALOSCGM =1100 9.5 XTALOSCGM =1101 10 XTALOSCGM =1110 10.5 XTALOSCGM =1111 11 XTALCAP = 000000 2 default XTALCAP = 111111 33 0.5 Note Specifications MAX. UNIT MHz MHz kΩ Datasheet AX5051 ...
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... MHz, 300 kHz from carrier 433 MHz, 2 MHz from carrier TYP. MAX. UNIT 16 MHz 940 MHz 470 Hz 100 50 kHz 200 500 15 30 µ µ -85 -90 -100 -110 dBc/Hz -90 -95 -105 -115 -80 -90 -105 -115 dBc/Hz -90 -95 -110 -122 Datasheet AX5051 ...
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... Notes 1. Additional low-pass filtering was applied to the antenna interface, see section 7: Application Information. Version 1.9 CONDITION MIN. TYP. ASK 1 PSK 10 FSK 1 TXRNG=1111 14 LOCURST=1 TXRNG=1111 16 LOCURST=1 -50 Note 1 -55 15 Specifications MAX. UNIT 600 600 kbps 250 dBm dBm dBc Datasheet AX5051 ...
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... FSK 50 kbps, notes 1 & 2 FSK 100 kbps, notes 1 & 3 PSK 200 kbps, notes 1 & 4 FSK 100 kbps, note 5 -3 FSK h=16 PSK -116 -115 -110 -104 -100 -98 MIN. TYP. MAX. UNIT 1 600 10 600 kbps 1 250 -100 -20 dBm -35 dBm - 0.625 dB 0 Datasheet AX5051 ...
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... MHz above the wanted signal 6. Sensitivities for the 433 MHz band are 1-2 dB better than those for the 868 MHz band Version 1.9 CONDITION MIN. TYP. 17 Specifications MAX. UNIT 30 Datasheet AX5051 ...
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... CLK low duration Tch CLK high duration Notes 1. For SPI access during power-down mode the period should be relaxed to 100ns. For a figure showing the SPI timing parameters see section 5.15: Serial Peripheral Interface (SPI). Version 1.9 CONDITION MIN. TYP Note MAX. UNIT Datasheet AX5051 ...
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... AX5051 sends and receives data via the SPI port in frames. This standard operation mode is called Frame Mode. Pre and post ambles as well as checksums can be generated automatically. Interrupts control the data flow between a controller and the AX5051. The AX5051 behaves as a SPI slave interface. Configuration of the the SPI interface ...
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... Automatic Frequency Control, both are described further down. Alternatively a single ended reference (TXCO, CXO) may be used. The CMOS levels should be applied to CLK16P via an AC coupling with the crystal oscillator enabled. Version 1.9 PWRMODE register. At power- not Datasheet AX5051 ...
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... The synthesizer loop bandwidth can be programmed, this serves three purposes: 1. Start-up time optimisation, start-up is faster for higher synthesizer loop bandwidths 2. TX spectrum optimisation, phase-noise at 300 kHz to 1 MHz distance from the carrier improves with lower synthesizer loop bandwidths Version 1.9 PWRMODE register is toggled. 21 Circuit Description Datasheet AX5051 ...
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... Switches between 868 MHz/915 MHz and 433 MHz bands FREQ Programming of the carrier frequency IFFREQHI, IFFREQLO Programming of the IF frequency PLLRANGING Initiate VCO auto-ranging and check results Version 1.9 FREQ registers. For operation in the PLLLOOP register must be programmed. PLLLOOP settings, for details see the Purpose Datasheet AX5051 ...
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... For detailed instructions how to program the digital channel filter and the demodulator see the AX5051 Programming Manual, an overview of the registers involved is given in the following table. The register setups typically must be done once at power-up of the device. Version 1.9 23 Circuit Description Datasheet AX5051 ...
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... These registers control the bit rate of the transmitter. These registers control the frequency deviation of the transmitter in FSK mode. The receiver does not explicitly need to know the frequency deviation, only the channel filter bandwidth has to be set wide enough for the complete modulation to pass. Programming Manual. Datasheet AX5051 ...
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... SPI access on MISO while the micro-controller shifts out the register address on MOSI. See the SPI interface section for details. This feature significantly reduces the number of SPI accesses necessary during transmit and receive. Version 1.9 25 Circuit Description Datasheet AX5051 ...
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... HDLC Mode Note: HDLC mode follows High-Level Data Link Control (HDLC, ISO 13239) protocol. HDLC Mode is the main framing mode of the AX5051. In this mode, the automatic packet delimiting, and optional packet correctness check by inserting and checking a cyclic redundancy check (CRC) field. ...
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... RSSI value can be computed at the expense of a few arithmetic operations on the micro-controller. Formulas for this computation can be found in the AX5051 Programming Manual. Version 1.9 Circuit Description of the radio bit rate, however AGCCOUNTER TRK_AMPLITUDE and the TRK_AMPLITUDE registers, a high Datasheet AX5051 27 register. ...
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... PA on BW=BITRATE ∆f=+f BW=(1+h) ⋅BITRATE deviation ∆Φ=180 BW=BITRATE 0 can demodulate signals with h < 32. AX5051 supports OQPSK. However, unless TRKFREQ to synchronize the receiver frequency × . FSKMUL AX5051 Programming Manual. For modulations other Max. Bitrate 600kBit/s 200kBit/s 600kBit/s Datasheet AX5051 ...
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... Synthesizer and transmitter are running. Do not switch into this mode before the synthesizer has completely settled on the transmit 1101 FULLTX frequency (in SYNTHTX mode), otherwise spurious spectral transmissions will occur. Version 1.9 29 Circuit Description Typical Idd 0.5 µA 200 µA 650 µ Datasheet AX5051 ...
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... Step PWRMODE[3:0] Remarks 1 POWERDOWN 2 STANDBY The settling time is dominated by the crystal used, typical value 3ms The synthesizer settling time is 5 – 50 µs depending on settings, see section AC 3 SYNTHRX Characteristics 4 FULLRX Data reception 5 POWERDOWN Version 1.9 Datasheet AX5051 ...
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... FIFO OVER FIFO UNDER SPI Timing Tss Tck TchTcl SCK MOSI R MISO Tssd Figure 3 Serial peripheral interface timing Version 1.9 AX5051 are programmed via the serial S3 S2 FIFO FULL FIFO EMPTY Tco 31 Circuit Description S1 S0 FIFOSTAT(1) FIFOSTAT(0) Tsh Tssz Datasheet AX5051 ...
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... No checks are made whether the programmed combination of bits makes sense! Bit 0 is always the LSB. Note Whole registers or register bits marked as reserved should be kept at their default values. Note All addresses not documented here must not be accessed, neither in reading nor in writing. Version 1.9 Datasheet AX5051 ...
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... Silicon Revision Scratch Register PWRMODE(3:0) Power Mode XTALOSCGM(3: Crystal Oscillator FIFO EMPTY FIFOCMD(1:0) FIFO Control FIFO Data IRQ Mask IRQ Request Interface Mode IFMODE(3:0) Must be set to 0000 SYSCLK(3:0) Pin Configuration 1 Pin Configuration 2 reserved IRQI reserved TST_PINS(1:0) must be set to 11 Datasheet AX5051 33 ...
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... CRC Initialization Data or Preamble SSREG SDS SREG Voltage Regulator Status Synthesizer Frequency Synthesizer Frequency Synthesizer Frequency Synthesizer Frequency FSK Frequency Deviation FSK Frequency Deviation FSK Frequency Deviation 2nd Frequency 2nd Frequency FLT(1:0) Synthesizer Loop Filter Settings VCOR(3:0) Synthesizer VCO Auto-Ranging Datasheet AX5051 ...
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... AGC Attack AGCDECAY(4:0) AGC Decay AGC Current Value CICSHIFT(4:0) CIC Shift Factor CIC Decimation Factor Datarate Datarate Timing Gain Timing Gain PHASEGAIN(3:0) Phase Gain FREQGAIN(3:0) Frequency Gain FREQGAIN2(3:0) Frequency Gain 2 AMPLGAIN(3:0) Amplitude Gain Amplitude Tracking Amplitude Tracking TRKPHASE(11:8) Phase Tracking Datasheet AX5051 35 ...
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... TRKFREQ(15:8) TRKFREQ(7: XTALCAP(5: reserved LOCURST reserved - - reserved - - reserved Phase Tracking Frequency Tracking Frequency Tracking Crystal oscillator tuning capacitance Synthesizer VCO current VCO_I[2:0] Must be set to 001 LOCURST Must be set to 1 REF_I[2:0] Reference adjust Misc RF settings RXIMIX(1:0) RXIMIX(1:0) must be set to 01 Datasheet AX5051 ...
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... VDD and VDD_IO pin. In order to reduce noise on the antenna inputs it is recommended to add the VDD pins close to the antenna interface. Version 1.9 1µF NC VDD VDD_IO GND AX5051 ANTP ANTN GND VDD Figure 4 Typical application diagram 37 Application Information NC IRQ TST3 MOSI MISO CLK Datasheet AX5051 ...
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... MHz 33 3 Version 1.9 AX5051 AX5051 is in transmit mode. A small antenna can be connected L3=L4 C2 C3=C5 [nH] [pF] [pF] 12 2.2 1.8 33 3.3 3 receive mode, and 50Ω single- CB ended equipment or antenna L5=L6 LB CA=CB C4=C6 [nH] [nH] [pF] [pF] 18 6.2 8.2 150 220 Datasheet AX5051 ...
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... The AX5051 has an integrated voltage regulator which generates a stable supply voltage VREG from the voltage applied at VDD_IO. Use VREG to supply all the VDD supply pins. Version 1.9 L3 dipole C1 C2 antenna L4 C1 L3=L4 [pF] [nH] 18 3.9 6 Application Information C2 [pF] 3.3 6.8 Datasheet AX5051 ...
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... Datum C and the seating plane are defined by the flat surface of the metallised terminal 5. Package surface shall be matte finish, Ra 1.6-2.2 6. Package warp shall be 0.050 maximum 7. Leadframe material is copper A194 8. Coplanarity applies to the exposed pad as well as the terminal 9. YYWWXX is the packaging lot code 10. RoHS Version 1.9 2 Datasheet AX5051 ...
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... Version 1.9 QFN28 Package Information Reflow Time Pb-Free Process 3 °C/sec max. T 150°C sMIN T 200°C sMAX t 60 – 180 sec min max. 25 ° to Peak T 217° – 150 sec L t 260° – 40 sec p 6°C/sec max. 41 Cooling Datasheet AX5051 ...
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... Clearance from edge of PCB thermal pad to PCB land, 0.2 mm minimum C = Clearance from PCB land edge to solder mask opening tight as possible to ensure that some solder mask remains between PCB pads D = PCB land length = QFN solder pad length + 0.1mm E = PCB land width = QFN solder pad width + 0.1 mm Datasheet AX5051 ...
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... No-clean flux is recommended since flux from underneath the thermal pad will be difficult to clean if water-soluble flux is used. Figure 8: Solder paste application on exposed pad Minimum 50% coverage Figure 9: Solder paste application on pins Version 1.9 QFN28 Package Information Maximum 62% coverage 80% coverage 43 Datasheet AX5051 ...
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... This product is not designed for use in life support appliances, devices systems where malfunction of this product can reasonably be expected to result in personal injury. AXSEM customers using or selling this product for use in such applications their own risk and agree to fully indemnify AXSEM for any damages resulting from such improper use or sale. Version 1.9 Datasheet AX5051 ...
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... Offenders will be held liable for the payment of damages. All rights reserved. Copyright © 2007 AXSEM AG Version 1.9 Contact Information Phone +41 44 882 17 07 Fax +41 44 882 17 09 Email sales@axsem.com www.axsem.com Datasheet AX5051 45 ...