AD8347ARU Analog Devices Inc, AD8347ARU Datasheet - Page 19

• Manufacturer Part Number: AD8347ARU
• Description: Quadrature Dmod 65MHz 28-Pin TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD8347ARU

• Package: 28TSSOP
• Device Type: Demodulator
• Maximum I/q Frequency: 65(Typ) MHz
• Modulation Type: Quadrature
• Typical Noise Figure: 11 dB
• Maximum Conversion Gain: 39.5(Typ) dB
• Rohs Status: RoHS non-compliant
• Function: Demodulator
• Lo Frequency: 800MHz ~ 2.7GHz
• Rf Frequency: 800MHz ~ 2.7GHz
• P1db: -30dBm
• Gain: 39.5dB
• Noise Figure: 11dB
• Current - Supply: 80mA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP

OPERATING THE VGA
A three-stage VGA sets the gain in the RF section. Two of the
three stages come before the mixer while the third amplifies the
mixer output. All three stages are driven in parallel. The gain
range of the first RF VGA and that of the second RF VGA
combined with the mixer are both −13 dB to +10 dB. The gain
range of the baseband VGA is −4 dB to +19.5 dB. Therefore, the
overall gain range from the RF input to the IMXO and QMXO
pins is −30 dB to approximately +39.5 dB.
The gain of the VGA is set by the voltage on the VGIN pin,
which is a high impedance input. The gain control function
(which is linear-in-dB) and linearity are shown in Figure 4 and
Figure 5 at 1.9 GHz. Note that the sense of the gain control
voltage is negative because as the gain control voltage ranges
from 0.2 V to 1.2 V, the gain decreases from +39.5 dB to −30 dB.
MIXER OUTPUT LEVEL AND DRIVE CAPABILITY
I- and Q-channel baseband outputs, IMXO and QMXO, are
low impedance outputs (R
V
IMXO/QMXO are limited by their current drive capability of
1.5 mA maximum. This allows for a 600 mV p-p swing into a
200 Ω load. At lower output levels, IMXO and QMXO can drive
smaller load resistances, subject to the same current limit.
VREF
, the voltage on Pin 14. The achievable output levels on
LO
100pF
Figure 47. Single-Ended LO Drive
100pF
200 Ω
OUT
@ 3 Ω) with bias levels equal to
LOIN
LOIP
AD8347
Rev. A | Page 19 of 28
These output stages are not, however, designed to directly drive
50 Ω loads.
OPERATING THE VGA IN AGC MODE
Although the VGA can be driven by an external source such as
a DAC, the AD8347 has an on-board sum of squares detector to
allow the AD8347 to operate in an automatic leveling mode.
Due to the nature of the detector, an input signal with a higher
peak-to-average ratio causes the AGC loop to settle with a
higher mixer output peak-to-peak voltage. In this data sheet,
peak-to-peak calculations assume a sine wave input when
referencing AGC operation.
The connections for operating in this mode are shown in
Figure 46. The two mixer outputs are connected to Detector
Input VDT1 and Detector Input VDT2. The summed detector
output drives an internal integrator which, in turn, delivers a
gain correction voltage to the VAGC pin. A 0.1 μF capacitor
from VAGC to ground sets the dominant pole of the integrator
circuit. VAGC, which should be connected to VGIN, adjusts
gain until an internal threshold is reached. This threshold
corresponds to a level at the IMXO and QMXO pins of approxi-
mately 8.5 mV rms. This level changes slightly as a function of
RF input power (see Figure 34). For a CW (sine wave) input,
this corresponds to approximately 24 mV p-p. If this signal is
applied directly to the subsequent baseband amplifier stage,
the final baseband output is 760 mV p-p differential. See the
Baseband Amplifiers section.
If the VGA gain is set from an external source, VDT1 and
VDT2 (the on-board detector inputs) are not used and are tied
to VREF.
AD8347