LFEC10E-3FN256C LATTICE SEMICONDUCTOR, LFEC10E-3FN256C Datasheet - Page 7

• Manufacturer Part Number: LFEC10E-3FN256C
• Description: FPGA LatticeEC Family 10200 Cells 340MHz 130nm (CMOS) Technology 1.2V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFEC10E-3FN256C

• Package: 256FBGA
• Family Name: LatticeEC
• Device Logic Units: 10200
• Maximum Internal Frequency: 340 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 195
• Ram Bits: 282624
• In System Programmability: Yes

Lattice Semiconductor
Figure 2-4. Slice Diagram
Table 2-1. Slice Signal Descriptions
1. See Figure 2-3 for connection details.
2. Requires two PFUs.
Function
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Control Signals
selected and
inverted per
slice in routing
Inter-PFU signal
Inter-PFU signal
Multi-purpose
Multi-purpose
Control signal
Control signal
Control signal
From
Routing
Data signals
Data signals
Data signals
Data signals
Data signal
Data signal
Interslice signals
Type
are not shown
CLK
LSR
CE
M0
M1
A1
B1
C1
D1
A0
C0
D0
B0
A0, B0, C0, D0 Inputs to LUT4
A1, B1, C1, D1 Inputs to LUT4
Signal Names
Q0, Q1
F0, F1
OFX0
OFX1
FCIN
FCO
LSR
CLK
M0
M1
CE
Different slice / PFU
Different slice / PFU
To / From
To / From
LUT4 &
CARRY
LUT4 &
CARRY
CO
CO
CI
CI
Multipurpose Input
Multipurpose Input
Clock Enable
Local Set/Reset
System Clock
Fast Carry In
LUT4 output register bypass signals
Register Outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT8
For the right most PFU the fast carry chain output
2-4
SUM
SUM
F
F
1
OFX0
Expansion
LUT
Mux
LatticeECP/EC Family Data Sheet
Slice
Description
D
D
2
MUX depending on the slice
Latch
Latch
FF/
FF/
Q1
Q0
OFX1
OFX0
F0
F1
To
1
Routing
Architecture