LP38691DT-2.5 National Semiconductor, LP38691DT-2.5 Datasheet - Page 13

• Manufacturer Part Number: LP38691DT-2.5
• Description: LDO Regulator Pos 2.5V 0.5A 3-Pin (2+Tab) TO-252 Rail
• Manufacturer: National Semiconductor
• Type: Linearr

Specifications of LP38691DT-2.5

• Package: 3TO-252
• Function: LDO
• Number Of Outputs: 1
• Input Voltage Range: 10 to 2.7 V
• Output Voltage: 2.5 V
• Maximum Output Current: 0.5 A
• Output Type: Fixed
• Accuracy: ±2 %
• Typical Dropout Voltage @ Current: 0.08@100mA|0.43@500mA V
• Operating Temperature: -40 to 125 °C
• Polarity: Positive

plane. Using a single point ground technique for the regulator
and it’s capacitors fixed the problem. Since high current flows
through the traces going into V
Kelvin connect the capacitor leads to these pins so there is
no voltage drop in series with the input and output capacitors.
LLP MOUNTING
The SDE06A (No Pullback) 6-Lead LLP package requires
specific mounting techniques which are detailed in National
Semiconductor Application Note # 1187. Referring to the sec-
tion PCB Design Recommendations in AN-1187 (Page 5), it
should be noted that the pad style which should be used with
the LLP package is the NSMD (non-solder mask defined)
type. Additionally, it is recommended the PCB terminal pads
to be 0.2 mm longer than the package pads to create a solder
fillet to improve reliability and inspection.
The input current is split between two V
two V
device can meet all specifications at the rated current.
The thermal dissipation of the LLP package is directly related
to the printed circuit board construction and the amount of
additional copper area connected to the DAP.
The DAP (exposed pad) on the bottom of the LLP package is
connected to the die substrate with a conductive die attach
adhesive. The DAP has no direct electrical (wire) connection
to any of the pins. There is a parasitic PN junction between
the die substrate and the device ground. As such, it is strongly
recommend that the DAP be connected directly to the ground
at device lead 2 (i.e. GND). Alternately, but not recommend-
ed, the DAP may be left floating (i.e. no electrical connection).
The DAP must not be connected to any potential other than
ground.
For the LP38691SD and LP38693SD in the SDE06A 6-Lead
LLP package, the junction-to-case thermal rating, θJC, is
10.4°C/W, where the case is the bottom of the package at the
center of the DAP. The junction-to-ambient thermal perfor-
mance for the LP38691SD and LP38693SD in the SDE06A
6-Lead LLP package, using the JEDEC JESD51 standards is
summarized in the following table:
RFI/EMI SUSCEPTIBILITY
RFI (radio frequency interference) and EMI (electromagnetic
interference) can degrade any integrated circuit’s perfor-
JESD 51-3
JESD 51-7
2-Layer
4-Layer
JEDEC
JEDEC
Board
Type
IN
pins must be connected together to ensure that the
Thermal
None
Vias
1
2
4
6
10.4°C/W
10.4°C/W
10.4°C/W
10.4°C/W
10.4°C/W
IN
and coming from V
θ
JC
IN
pins, 1 and 6. The
237° C/W
74° C/W
60° C/W
49° C/W
45° C/W
θ
JA
OUT
,
13
mance because of the small dimensions of the geometries
inside the device. In applications where circuit sources are
present which generate signals with significant high frequen-
cy energy content (> 1 MHz), care must be taken to ensure
that this does not affect the IC regulator.
If RFI/EMI noise is present on the input side of the regulator
(such as applications where the input source comes from the
output of a switching regulator), good ceramic bypass capac-
itors must be used at the input pin of the IC.
If a load is connected to the IC output which switches at high
speed (such as a clock), the high-frequency current pulses
required by the load must be supplied by the capacitors on
the IC output. Since the bandwidth of the regulator loop is less
than 100 kHz, the control circuitry cannot respond to load
changes above that frequency. This means the effective out-
put impedance of the IC at frequencies above 100 kHz is
determined only by the output capacitor(s).
In applications where the load is switching at high speed, the
output of the IC may need RF isolation from the load. It is
recommended that some inductance be placed between the
output capacitor and the load, and good RF bypass capacitors
be placed directly across the load.
PCB layout is also critical in high noise environments, since
RFI/EMI is easily radiated directly into PC traces. Noisy cir-
cuitry should be isolated from "clean" circuits where possible,
and grounded through a separate path. At MHz frequencies,
ground planes begin to look inductive and RFI/ EMI can cause
ground bounce across the ground plane. In multi-layer PCB
applications, care should be taken in layout so that noisy
power and ground planes do not radiate directly into adjacent
layers which carry analog power and ground.
OUTPUT NOISE
Noise is specified in two ways: Spot Noise or Output Noise
Density is the RMS sum of all noise sources, measured at
the regulator output, at a specific frequency (measured with
a 1Hz bandwidth). This type of noise is usually plotted on a
curve as a function of frequency. Total Output Noise or
Broad-Band Noise is the RMS sum of spot noise over a
specified bandwidth, usually several decades of frequencies.
Attention should be paid to the units of measurement. Spot
noise is measured in units µV/root-Hz or nV/root-Hz and total
output noise is measured in µV(rms)
The primary source of noise in low-dropout regulators is the
internal reference. Noise can be reduced in two ways: by in-
creasing the transistor area or by increasing the current drawn
by the internal reference. Increasing the area will decrease
the chance of fitting the die into a smaller package. Increasing
the current drawn by the internal reference increases the total
supply current (ground pin current).
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