8305AGILF Integrated Device Technology (Idt), 8305AGILF Datasheet - Page 10

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8305AGILF

Manufacturer Part Number
8305AGILF
Description
Clock Driver 2-IN LVCMOS/LVTTL 16-Pin TSSOP Tube
Manufacturer
Integrated Device Technology (Idt)
Datasheet

Specifications of 8305AGILF

Package
16TSSOP
Configuration
1 x 2:1
Input Signal Type
HCSL/LVCMOS/LVDS/LVHSTL/LVPECL/LVTTL/SSTL
Maximum Output Frequency
350 MHz
Operating Supply Voltage
3.3 V

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W
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
8305AGI
IRING THE
D
IFFERENTIAL
I
F
NPUT TO
IGURE
Single Ended Clock Input
2. S
A
A
PPLICATION
CCEPT
INGLE
E
C1
0.1u
S
NDED
V_REF
INGLE
DD
LVCMOS-
www.idt.com
/2 is
S
L
IGNAL
OW
E
10
I
NDED
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
NFORMATION
S
1K
D
R1
1K
R2
KEW
RIVING
VDD
L
TO
EVELS
, 1-
CLK
nCLK
-LVCMOS/LVTTL F
D
IFFERENTIAL
TO
-4, M
I
NPUT
ULTIPLEXED
DD
= 3.3V, V_REF should be 1.25V
ANOUT
ICS8305I
D
IFFERENTIAL
REV. B JULY 29, 2010
B
UFFER
/

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