83056AGI-01LF Integrated Device Technology (Idt), 83056AGI-01LF Datasheet - Page 5

• Manufacturer Part Number: 83056AGI-01LF
• Description: Clock Multiplexer 2-IN LVCMOS/LVTTL 20-Pin TSSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 83056AGI-01LF

• Package: 20TSSOP
• Configuration: 6 x 2:1
• Input Signal Type: LVCMOS|LVTTL
• Maximum Output Frequency: 250 MHz
• Operating Supply Voltage: 2.5|3.3 V

AC Electrical Characteristics
Table 5A. AC Characteristics, V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Measured from V
NOTE 2: Driving only one input clock.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Table 5B. AC Characteristics, V
See notes in Table 5A above.
IDT™ / ICS™ 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
Symbol
f
tp
tp
tjit
tsk(i)
tsk(o)
tsk(pp)
t
odc
MUX
Symbol
f
tp
tp
tjit
tsk(i)
tsk(o)
tsk(pp)
t
odc
MUX
MAX
R
MAX
R
ICS83056I-01
6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
LH
HL
LH
HL
/ t
/ t
F
F
ISOLATION
ISOLATION
Parameter
Output Frequency
Propagation Delay, Low-to-High;
NOTE 1
Propagation Delay, High-to-Low;
NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 2
Input Skew; NOTE 3
Output Skew: NOTE 4
Part-to-Part Skew; NOTE 3, 5
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
Parameter
Output Frequency
Propagation Delay, Low-to-High;
NOTE 1
Propagation Delay, High-to-Low;
NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 2
Input Skew; NOTE 3
Output Skew: NOTE 4
Part-to-Part Skew; NOTE 3, 5
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
DD
/2 of the input to V
DD
DD
= V
= 3.3V ± 5%, V
DDO
DDO
= 3.3V ± 5%, T
/2 of the output.
155.52MHz, Integration Range:
155.52MHz, Integration Range:
DDO
= 2.5V ± 5%, T
Test Conditions
Test Conditions
12kHz – 20MHz
f
12kHz – 20MHz
OUT
A
20% to 80%
20% to 80%
5
= -40°C to 85°C
100MHz
100MHz
≤ 175MHz
A
= -40°C to 85°C
Minimum
Minimum
300
300
1.8
2.0
2.1
2.3
40
40
ICS83056AGI-01 REV. A JANUARY 29, 2009
Typical
Typical
0.18
0.14
2.5
2.6
2.6
2.7
45
45
Maximum
Maximum
DDO
250
145
130
800
800
250
100
130
800
800
3.2
3.2
3.1
3.1
60
60
/2.
Units
Units
MHz
MHz
dB
dB
ps
ns
ns
ps
ps
ps
ps
ps
ns
ns
ps
ps
ps
ps
%
%