MAX7313AEG+ Maxim Integrated Products, MAX7313AEG+ Datasheet - Page 8

• Manufacturer Part Number: MAX7313AEG+
• Description: I/O Expander 24-Pin QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX7313AEG+

• Package: 24QSOP
• Operating Temperature: -40 to 125 °C

only as an input. A pullup resistor, typically 4.7kΩ, is
required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX7313
7-bit slave address plus R/W bit, a register address
byte, one or more data bytes, and finally a STOP condi-
tion (Figure 3).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
16-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection
Figure 3. Start and Stop Conditions
Figure 4. Bit Transfer
Figure 5. Acknowledge
Figure 6. Slave Address
8
TRANSMITTER
SDA
SCL
SDA
SCL
RECEIVER
_______________________________________________________________________________________
CONDITION
SDA BY
SDA BY
START
SDA
SCL
SCL
S
CONDITION
START
DATA LINE STABLE;
S
DATA VALID
MSB
A6
1
CHANGE OF DATA
ALLOWED
A5
2
Start and Stop Conditions
FOR ACKNOWLEDGE
CLOCK PULSE
A4
8
CONDITION
A3
9
STOP
P
A2
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX7313, the device gen-
erates the acknowledge bit because the MAX7313 is
the recipient. When the MAX7313 is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
The MAX7313 has a 7-bit long slave address (Figure 6).
The eighth bit following the 7-bit slave address is the
R/W bit. The R/W bit is low for a write command, high
for a read command.
The slave address bits A6 through A0 are selected by
the address inputs AD0, AD1, and AD2. These pins can
be connected to GND, V+, SDA, or SCL. The MAX7313
has 64 possible slave addresses (Table 1) and, there-
fore, a maximum of 64 MAX7313 devices can be con-
trolled independently from the same interface.
A write to the MAX7313 comprises the transmission of
the MAX7313’s slave address with the R/W bit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte. The command
byte determines which register of the MAX7313 is to be
written to by the next byte, if received (Table 2). If a
STOP condition is detected after the command byte is
received, then the MAX7313 takes no further action
beyond storing the command byte.
A1
Message Format for Writing the MAX7313
LSB
A0
R/W
Slave Address
ACK
Acknowledge
Bit Transfer