MAX1303BEUP+ Maxim Integrated Products, MAX1303BEUP+ Datasheet - Page 14

• Manufacturer Part Number: MAX1303BEUP+
• Description: ADC Single SAR 115KSPS 16-Bit Serial 20-Pin TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1303BEUP+

• Package: 20TSSOP
• Resolution: 16 Bit
• Sampling Rate: 115 KSPS
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 4|2
• Digital Interface Type: Serial (SPI, QSPI, Microwire)
• Input Type: Voltage
• Signal To Noise Ratio: 90(Typ) dB
• Polarity Of Input Voltage: Unipolar|Bipolar

To maintain a low-noise environment, the MAX1302 and
MAX1303 provide separate power supplies for each
section of circuitry. Table 1 shows the four separate
power supplies. Achieve optimal performance using
separate AV
Alternatively, connect AV
together as close to the device as possible for a conve-
nient power connection. Connect AGND1, AGND2,
AGND3, DGND, and DGNDO together as close to the
device as possible. Bypass each supply to the corre-
sponding ground using a 0.1µF capacitor (Table 1). If
significant low-frequency noise is present, add a 10µF
capacitor in parallel with the 0.1µF bypass capacitor.
The MAX1302/MAX1303 ADCs feature a fully differen-
tial, successive-approximation register (SAR) conver-
sion technique and an on-chip T/H block to convert
voltage signals into a 16-bit digital result. Both single-
ended and differential configurations are supported
with programmable unipolar and bipolar signal ranges.
8-/4-Channel, ±V
Serial 16-Bit ADCs
Table 1. MAX1302/MAX1303 Power Supplies and Bypassing
Table 2. Analog Input Configuration Byte
14
NUMBER
SUPPLY/GROUND
BIT
______________________________________________________________________________________
DV
7
6
5
4
3
2
1
0
AV
AV
DV
DDO
DD2
DD1
POWER
DD
/DGNDO
/AGND2
/AGND1
/DGND
DD1
DIF/SGL
START
NAME
C2
C1
C0
, AV
R2
R1
R0
DD2
Start Bit. The first logic 1 after CS goes low defines the beginning of the analog input configuration byte.
Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5).
Differential or Single-Ended Configuration Bit. DIF/SGL = 0 configures the selected analog input channel
for single-ended operation. DIF/SGL = 1 configures the channel for differential operation. In single-ended
mode, input voltages are measured between the selected input channel and AGND1, as shown in
Table 4. In differential mode, the input voltages are measured between two input channels, as shown in
Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6.
Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.
, DV
SUPPLY VOLTAGE
DD1
DD
Converter Operation
4.75 to 5.25
4.75 to 5.25
4.75 to 5.25
RANGE (V)
2.7 to 5.25
, and DV
, AV
Power Supplies
DD2
REF
DDO
, and DV
supplies.
Multirange Inputs,
TYPICAL SUPPLY
CURRENT (mA)
DD
17.5
0.2
3.0
0.9
The MAX1302/MAX1303 feature a switched-capacitor
T/H architecture that allows the analog input signal to be
stored as charge on sampling capacitors. See Figures 2,
3, and 4 for T/H timing and the sampling instants for
each operating mode. The MAX1302/MAX1303 analog
input circuitry buffers the input signal from the sampling
capacitors, resulting in a constant analog input imped-
ance with varying input voltage (Figure 5).
Select differential or single-ended conversions using the
associated analog input configuration byte (Table 2).
The analog input signal source must be capable of dri-
ving the ADC’s 6kΩ input resistance (Figure 6).
Figure 6 shows the simplified analog input circuit. The
analog inputs are ±6V fault tolerant and are protected
by back-to-back diodes. The summing junction voltage,
V
voltage:
V
SJ
SJ
DESCRIPTION
, is a function of the channel’s input common-mode
=
⎛
⎜
⎝
Digital I/O
Analog Circuitry
Analog Circuitry
Digital Control Logic and
Memory
R
1
CIRCUIT SECTION
R
+
1
R
2
⎞
⎟ ×
⎠
2 375
.
Track-and-Hold Circuitry
V
Analog Input Circuitry
+
⎛
⎜
⎝
1
0.1µF to DGNDO
0.1µF to AGND2
0.1µF to AGND1
0.1µF to DGND
+
⎛
⎜
⎝
R
1
BYPASSING
R
+
1
R
2
⎞
⎟
⎠
⎞
⎟ ×
⎠
V
CM