ADC0809CCV National Semiconductor, ADC0809CCV Datasheet - Page 4

• Manufacturer Part Number: ADC0809CCV
• Description: ADC Single SAR 10KSPS 8-Bit Parallel 28-Pin PLCC Rail
• Manufacturer: National Semiconductor

Specifications of ADC0809CCV

• Package: 28PLCC
• Resolution: 8 Bit
• Sampling Rate: 10 KSPS
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 8
• Digital Interface Type: Parallel
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar
• No. Of Pins: 28
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Package / Case: 28-PLCC
• Rohs Compliant: No

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I
I
I
DATA OUTPUTS AND EOC (INTERRUPT)
V
V
V
I
t
t
t
t
t
t
t
t
t
f
t
C
C
IN(1)
IN(0)
CC
OUT
STCLK
WS
WALE
s
H
D
H1
1H
c
c
EOC
OUT(1)
OUT(0)
OUT(0)
IN
OUT
Electrical Characteristics – Timing Specifications
Timing Specifications V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: A Zener diode exists, internally, from V
Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop
greater than the V
by more than 100 mV, the output code will be correct. To achieve an absolute 0V
of 4.900 V
Note 5: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. See Figure 3. None of these A/Ds requires a zero or full-scale adjust.
However, if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference
voltages can be adjusted to achieve this. See Figure 13.
Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has
little temperature dependence (Figure 6). See paragraph 4.0.
Note 7: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 8: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Symbol
, t
, t
Symbol
H0
0H
DC
over temperature variations, initial tolerance and loading.
Start Time Delay from Clock
Minimum Start Pulse Width
Minimum ALE Pulse Width
Minimum Address Set-Up Time
Minimum Address Hold Time
Analog MUX Delay Time From ALE R
OE Control to Q Logic State
OE Control to Hi-Z
Conversion Time
Clock Frequency
EOC Delay Time
Input Capacitance
TRI-STATE Output Capacitance
CC
Logical “1” Input Current (The Control
Inputs)
Logical “0” Input Current (The Control
Inputs)
Supply Current
Logical “1” Output Voltage
Logical “0” Output Voltage
Logical “0” Output Voltage EOC
TRI-STATE Output Current
n supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog V
Parameter
CC
=V
Parameter
REF(+)
=5V, V
CC
to GND and has a typical breakdown voltage of 7 V
REF(−)
=GND, t
(Figure 5)
(Figure 5)
(Figure 5)
(Figure 5)
(Figure 5)
C
C
f
(Figure 5)
At Control Inputs
At TRI-STATE Outputs
c
=640 kHz, (Figure 5) (Note 7)
S
L
L
=50 pF, R
=10 pF, R
=0Ω (Figure 5)
V
V
f
V
I
I
V
V
CLK
O
O
IN
IN
CC
O
O
=1.6 mA
=1.2 mA
I
I
r
=5V
=0
OUT
OUT
=15V
=0
=t
=640 kHz
= 4.75V
f
=20 ns and T
Conditions
L
L
= −360µA
= −10µA
=10k (Figure 8)
=10k (Figure 8)
Conditions
4
DC
to 5V
DC
A
=25°C unless otherwise noted.
input voltage range will therefore require a minimum supply voltage
DC
−1.0
Min
.
2.4
4.5
−3
MIn
300
90
10
0
Typ
0.3
IN
Typ
100
100
125
125
100
640
25
25
10
10
does not exceed the supply voltage
1
8 + 2 μS
Max
0.45
0.45
1.0
3.0
1280
Max
900
200
200
250
250
116
3
2.5
50
50
15
15
Periods
Units
Units
Clock
mA
μA
μA
μA
μA
kHz
V
V
V
V
pF
pF
ns
ns
ns
ns
ns
μs
ns
ns
μs