AT84CS001VTPY E2V, AT84CS001VTPY Datasheet - Page 7

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AT84CS001VTPY

Manufacturer Part Number
AT84CS001VTPY
Description
Demultiplexer 240-Pin EBGA
Manufacturer
E2V
Datasheet

Specifications of AT84CS001VTPY

Package
240EBGA
Power Supply Type
Analog|Digital
Typical Supply Current
600 mA
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
2.375|3.15 V
Maximum Operating Supply Voltage
2.625|3.45 V
3.2
3.3
3.4
e2v semiconductors SAS 2009
Programmable DMUX Ratio
Additional Bit (IOR,IORN)
Clock Type Selection CLKTYPE and DRTYPE
The demultiplexer ratio is programmable through the RS ratio selection signal:
Table 3-3.
Figure 3-3.
Note:
Figure 3-4.
When a signal is applied on IOR and IORN, the additional bit is activated. It can be used to process the
out-of-range bit from the ADC, in which case the DMUX features an 11-bit input/output data stream.
IOR, IORN is demultiplexed by the selected DMUX ratio:
Note:
Two modes for the input and output clock type can be selected by way of the CLKTYPE and DRTYPE
single-ended digital inputs.
• In 1:4 ratio, AOR/DRAN, AORN/DRA, BOR/DRBN, BORN/DRB, COR/DRCN, CORN/DRC and
• In 1:2 ratio, AOR/DRAN, AORN/DRA and BOR/DRBN, BORN/DRB output this signal at half its initial
DOR/DRDN, DORN/DRD output this signal at a quarter of its initial speed.
speed.
Ports C & D data have undetermined level. They can be left unconnected.
In staggered output mode:
(AORN/DRA, AOR/DRAN), (BORN/DRB, BOR/DRBN), (CORN/DRC, COR/DRCN) and (DORN/DRD,
DOR/DRDN) are used as the Data Ready signal (output clock) for each port. In this mode the additional bit
is disabled.
DMUX Ratio Selection Settings
DMUX in 1:2 Ratio
DMUX in 1:4 Ratio
RS
Input Words:
1, 2, 3, 4, 5, 6, 7, 8…
Input Words:
1, 2, 3, 4, 5, 6, 7, 8…
0
1
1:2
1:4
Output Words:
Port A
Port B
Port C
Port D
Output Words:
Port A
Port B
Port C
Port D
DMUX Ratio
1:2
1:4
1
2
Not used
Not used
1
2
3
4
3
4
5
6
7
8
5
9
0809E–BDC–05/09
AT84CS001
7

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